Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Design of 4×4 Block Parallel Interpolation Motion Compensation Architecture for 4K UHD H.264/AVC Decoder

4K UHD급 H.264/AVC 복호화기를 위한 4×4 블록 병렬 보간 움직임보상기 아키텍처 설계

  • Lee, Kyung-Ho (Department of Computer Engineering, Kwangwoon University) ;
  • Kong, Jin-Hyeung (Department of Computer Engineering, Kwangwoon University)
  • 이경호 (광운대학교 컴퓨터공학과) ;
  • 공진흥 (광운대학교 컴퓨터공학과)
  • Received : 2013.01.04
  • Published : 2013.05.25
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

본 연구에서는 4K UHD($3840{\times}2160$) 영상을 실시간 복호화하기 위한 $4{\times}4$ 블록 병렬 보간 H.264/AVC 움직임보상기를 제안한다. 연산처리 성능을 향상시키기 위해 보간 연산을 $4{\times}4$ 블록 단위로 병렬화시켰으며, 병렬 보간 연산에서 필요한 메모리 대역폭을 확장하기 위해 $9{\times}9$개의 메모리 어레이를 가진 2D 캐쉬 버퍼 구조를 설계하였다. 그리고 2D 캐쉬 버퍼는 검색영역 간 재사용 기법을 적용하여 참조화소의 중복저장을 최소화하였으며, $4{\times}4$ 블록 병렬 보간 필터는 3단(수평 수직 1/2부화소, 대각선 1/2부화소, 1/4부화소) 평면 보간 연산 파이프라인 구조로 설계하여 연산회로를 고속화시켰다. 0.13um 공정에서 시뮬레이션한 결과, 161K게이트의 H.264/AVC 움직임보상기는 동작주파수 150MHz에서 4K UHD급 동영상을 초당 72프레임으로 실시간 처리하는 성능을 보였다.

Keywords

References

  1. Xue Quan, Liu Jilin, "H.264/AVC Baseline Profile Decoder Optimization on Independent Platform", WiCOM, 2005
  2. RongGang Wang, JinTao Li, Chao Huang, "Motion compensation memory access optimization strategies for H.264/AVC decoder", ICASSP, 2005.
  3. Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Chen-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, and Tihao Chiang, "A Platform-Based MPEG-4 Advanced Video Coding(AVC) Decoder with Block Level Pipelining", PCM, 2003.
  4. Yu Li, Yanmei Qu, Yun He, "Memory Cache Based Motion compensation Architecture for HDTV H.264/AVC Decoder", Department of Electronic Engineering, Tsinghua University, 2007.
  5. Deng Lei, Gao Wen Hu MingZeng, Ji Zhen Zhou, "An Efficient VLSI Architecture for MC interpolation in AVC Video coding", ESA/VLSI, 2004.
  6. Ronggang Wang, Mo Li, Jintao Li, Yongdong Zhang, "High Throughput and Low Memory Access Sub-pixel Interpolation Architecture for H.264/AVC HDTV Decoder", IEEE Transactions on Consumer Electronics, 2005.
  7. Sheng Zen Wang, "A new motion compensation design for H.264/AVC decoder ", ISCAS, 2005.
  8. Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang, "Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application", IEEE ICASSP 2006 14-19 May 2006.
  9. Ping Chao, Youn-Long Lin, "A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding", ISCAS 2008, pp : 256-259
  10. 이찬호, "H.264 복호기를 위한 효율적인 예측 연산기 설계", 대한전자공학회, 전자공학회논문지-SD 46(7), 2009.7, pp : 47-52
  11. Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture", IEEE Transactions on Circuits and Systems for Video Technology. Jan 2002 Vol.12 pp : 61-72 https://doi.org/10.1109/76.981846