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http://dx.doi.org/10.5573/ieek.2013.50.5.102

A Design of 4×4 Block Parallel Interpolation Motion Compensation Architecture for 4K UHD H.264/AVC Decoder  

Lee, Kyung-Ho (Department of Computer Engineering, Kwangwoon University)
Kong, Jin-Hyeung (Department of Computer Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.5, 2013 , pp. 102-111 More about this Journal
Abstract
In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.
Keywords
H.264/AVC Decoder; Motion Compensation; $4{\times}4$ Block Parallel; 2D Cache buffer; Pipeline;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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