• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.219-225
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• 2013

Program and erase characteristics of the elliptic gate all around (e-GAA) SONOS cell have been studied as the variation of eccentricity of the channel. An analytic program and erase model for the elliptic GAA SONOS cell is proposed and evaluated. The model shows that the ISPP (incremental-step-pulse programming) property is changed non-linearly as the eccentricity of the e-GAA SONOS cell is increased. It is differently from the well known linear relationship for that of 2D SONOS and even 3D circular SONOS cell with program bias. We can find that the simulation results of ISPP characteristics are in accord with the experimental data.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1654-1659
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• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Journal of recreation and landscape
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• v.12 no.4
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• pp.1-10
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• 2018

This study is about the investigation of the walking environment of the First Experimental Elementary School in Shapingba District of Chongqing City and the Zaozilanya Elementary School in Yuzhong District and the analysis of the pedestrian's consciousness. The improvement plan is obtained by comparing and analyzing the walking environment around the school. The survey results are as follows. According to the survey results of the walking environment around the school, the sidewalks of the two schools are relatively narrow, and there are more pedestrians crossing the road. There is a phenomenon of parking in both schools. The phenomenon of parking in Zaozilanya Elementary School is even more serious. In investigating the most important elements of the school's pedestrian environment, the setting of the signpost, the setting of the crosswalk and signal lights, the setting of the fence, the setting of the vehicle's deceleration facilities, and the control of the school gate are all necessary. Therefore, in order to create a safe and comfortable improvement plan for the surrounding environment of the school, first of all, in the improvement of the facilities around the school, the setting of the fence, the setting of the speed bump, the improvement of the crosswalk and the signal light. Second, in terms of restrictions, the scope of protection around the school needs to be expanded, and restrictions on parking and restrictions on vehicle traffic need to be implemented. Third, in terms of education and publicity, it is not only necessary to provide safety guidance for students to go to school, but also to provide drivers with driving safety education and publicity.

• Journal of Information Display
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• v.2 no.3
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• pp.66-71
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• 2001

MCFEDs (MOSFET-Contoolled Field Emission Displays) were fabricated to evaluate the validity of MCFEA for display application. The electrical properties of FEAs (Field Emitter Arrays), HVMOSFETs (High-Voltage MOSFETs), and MCFEAs (MOSFET-Controlled Field Emitter Arrays) were measured. The extraction gate voltage of the FEAs to obtain the anode current of 10 nA/tip was around 71 V. The breakdown voltages of the HVMOSFETs were above 81 V for all the samples. The I-V characteristics of the MCFEAs showed that the emission currents of the FEAs were well controlled depending on the control gate voltages of the HVMOSFETs. To avoid the harmful effects during the packaging process, the performance of the MCFEDs was evaluated in a high vacuum chamber. The emission images of the MCFEDs were controlled through very-through operation. From the comparison with a conventional FED, it was proven that the poor uniformity of FED could be improved through the integration with HVMOSFET.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.331-331
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• 2009

Hafnium oxide ($HfO_2$) attracted by one of the potential candidates for the replacement of si-based oxides. For applications of the high-k gate dielectric material, high thermodynamic stability and low interface-trap density are required. Furthermore, the amorphous film structure would be more effective to reduce the leakage current. To search the gate oxide materials, metal-insulator-metal (MIM) capacitors was fabricated by pulsed laser deposition (PLD) on indium tin oxide (ITO) coated glass with different oxygen pressures (30 and 50 mTorr) at room temperature, and they were deposited by Au/Ti metal as the top electrode patterned by conventional photolithography with an area of $3.14\times10^{-4}\;cm^2$. The results of XRD patterns indicate that all films have amorphous phase. Field emission scanning electron microscopy (FE-SEM) images show that the thickness of the $HfO_2$ films is typical 50 nm, and the grain size of the $HfO_2$ films increases as the oxygen pressure increases. The capacitance and leakage current of films were measured by a Agilent 4284A LCR meter and Keithley 4200 semiconductor parameter analyzer, respectively. Capacitance-voltage characteristics show that the capacitance at 1 MHz are 150 and 58 nF, and leakage current density of films indicate $7.8\times10^{-4}$ and $1.6\times10^{-3}\;A/cm^2$ grown at 30 and 50 mTorr, respectively. The optical properties of the $HfO_2$ films were demonstrated by UV-VIS spectrophotometer (Scinco, S-3100) having the wavelength from 190 to 900 nm. Because films show high transmittance (around 85 %), they are suitable as transparent devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.773-776
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• 2014

In this work, analog performances of silicon nanowire MOSFET with different length and channel width have been measured. The channel widths are 20nm, 30nm, 80nm, 130nm and lengths are 250nm, 300nm, 350nm, 500nm. temperatures $30^{\circ}C$, $50^{\circ}C$, $75^{\circ}C$, $100^{\circ}C$ have been measured. The trans-conductance, early voltage, gain, drain current and mobility have been characterized as a function of temperature. The mobility has been enhanced with wider channel width but it has been reduced with longer length and higher temperature. The trans-conductance has been increased with wider channel width. The early voltage has been enhanced with increase of gate length and temperature but it has been reduced with wider width. Therefore, gain has been enhanced with increase of gate longer length and wider width but it has been reduced with higher temperature.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.277-279
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• 2016

Nanowire-FET은 Gate-All-Around (GAA) 구조로 차세대 반도체 소자 구조로 여겨지고 있다. Nanowire-FET은 채널 두께에 따라 $I_D-V_G$ curve에 매우 중요한 영향을 끼친다. 따라서 본 논문은, Edison 시뮬레이션을 이용하여 Nanowire-FET의 Silicon Thickness에 따른 여러 특성을 비교하여 최적 Silicon Thickness에 대해 연구하였다.