• 전기학회논문지
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• 제65권10호
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• pp.1664-1671
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• 2016

This paper presents the analysis of the gate-source voltage of the gallium nitride high electronic mobility transistor (GaN HEMT) in the half bridge structure focused on the mutual effects of two switching operation. Especially low side gate-source voltage is analyzed mathematically according to the high side switch turn-on and turn-off operation. Moreover, the influence of each gate resistance and parasitic component on the switching characteristic of other side switch is investigated, and the formula, simulation and experimental results are compared with theoretical data.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권4호
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• pp.208-212
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• 2004

In this paper, the characteristics of co-sputtered Ru-Zr metal alloy as gate electrode of MOS capacitors have been investigated. The atomic compositions of alloy were varied by using the combinations of relative sputtering power of Ru and .Zr. C-V and I-Vcharacteristics of MOS capacitors were measured to find the effective oxide thickness and work function. The alloy made of about 50% of Ru and 50% of Zr exhibited an adequate work function for nMOS. C-V and I-V measurements after 600 and $700^{\circ}C$ rapid thermal annealing were performed to prove the thermal and chemical stability of the Ru-Zr alloy film. Negligible changes in the accumulated capacitance and work function before and after annealing were observed. Sheet resistance of Ru-Zr alloy was lower than that of poly-silicon. It can be concluded that the Ru-Zr alloy can be a possible substitute for the poly-silicon used as a gate of nMOS.

• 한국재료학회지
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• 제13권11호
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• 한국전기전자재료학회논문지
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• 제36권4호
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• pp.385-390
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• 2023

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권3호
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• pp.161-166
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• 1999

We investigate the device characteristics of the separated shorted-anode LIGBT (SSA-LIGBT), which suppresses effectively the negative differential resistance regime, by 2-dimensional numerical simulation. The SSA-LIGBT increases the pinch resistance by employing the highly resistive n-drift region as an electron conduction path instead of the lowly resistive n buffer region of the conventional SA-LIGBT. The negative differential resistance regime of the SSA-LIGBT is significantly suppressed as compared with that of the conventional SA-LIGBT. The SSA-LIGBT shows the lower forward voltage drop than that of the conventional SA-LIGBT.

• 조명전기설비학회논문지
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• 제27권3호
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• pp.55-64
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• 2013

In this paper, a new topology which can add a small reactor in series to a condenser-bank type reactive power compensator to limit current is proposed. And also the proposed topology can add or remove a power condenser safely without any addition of inrush-current suppression resistance. The proposed method tests variable resistance of the drain source of a switching device which is controlled by gate voltage in a two-way switch with a diode rectifier and FET switch. In other words, the proposed method is a inrush-current suppression method with the structure of variable resistance. In particular, the proposed method creates smooth current without any resonance in inrush-current as well as is not limited by the time of switch on and off.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• 전기전자학회논문지
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• 제22권1호
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• pp.180-184
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• 2018

산화갈륨 ($Ga_2O_3$)과 탄화규소 (SiC)는 넓은 밴드 갭 ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV)과 높은 임계전압을 갖는 물질로서 높은 항복 전압을 허용한다. 수직 DMOSFET 수평구조에 비해 높은 항복전압 특성을 갖기 때문에 고전압 전력소자에 많이 적용되는 구조이다. 본 연구에서는 2차원 소자 시뮬레이션 (2D-Simulation)을 사용하여 $Ga_2O_3$와 4H-SiC 수직 DMOSFET의 구조를 설계하였으며, 항복전압과 저항이 갖는 trade-off에 관한 파라미터를 분석하여 최적화 설계하였다. 그 결과, 제안된 4H-SiC와 $Ga_2O_3$ 수직 DMOSFET구조는 각각 ~1380 V 및 ~1420 V의 항복 전압을 가지며, 낮은 게이트 전압에서의 $Ga_2O_3-DMOSFET$이 보다 낮은 온-저항을 갖고 있지만, 게이트 전압이 높으면 4H-SiC-DMOSFET가 보다 낮은 온-저항을 갖을 수 있음을 확인하였다. 따라서 적절한 구조와 gate 전압 rating에 따라 소자 구조 및 gate dielectric등에 대한 심화 연구가 요구될 것으로 판단된다.