• Journal of electromagnetic engineering and science
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• 제13권2호
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• pp.127-133
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• 2013

We examined the scaling effects of a number of gate_fingers (N) and gate_widths (w) on the high-frequency characteristics of $0.1-{\mu}m$ metamorphic high-electron-mobility transistors. Functional relationships of the extracted small-signal parameters with total gate widths ($w_t$) of different N were proposed. The cut-off frequency ($f_T$) showed an almost independent relationship with $w_t$; however, the maximum frequency of oscillation ($f_{max}$) exhibited a strong functional relationship of gate-resistance ($R_g$) influenced by both N and $w_t$. A greater $w_t$ produced a higher $f_{max}$; but, to maximize $f_{max}$ at a given $w_t$, to increase N was more efficient than to increase the single gate_width.

• 전자공학회논문지
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• 제51권12호
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• pp.59-65
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• 2014

다양한 게이트 핑거 수(Nf)의 MOSFET에 대한 두 종류의 입력 저항이 $S_{11}$-parameter와 $Z_{11}$-parameter으로부터 변환 되어 저주파 영역에서 측정되었다. 본 연구에서 사용된 $Nf{\leq}64$의 범위에서 $S_{11}$-parameter로부터 추출된 1/Nf 종속 입력저항은 $Z_{11}$-parameter로부터 추출된 입력 저항보다 훨씬 낮은 값을 보여주며, 이러한 1/Nf 종속성은 MOSFET의 등가회로로부터 유도된 Nf 종속 비선형 방정식으로부터 이론적으로 증명하였다.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• ETRI Journal
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• 제26권1호
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• pp.7-13
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• 2004

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.247-252
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• 2012

IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.581-582
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• 2006

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.9-12
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• 2004

This paper investigated the stability of Ta-Mo alloy on thin gate dielectric. Ta-Mo alloy was deposited by using co-sputtering process after thermal growing of 3.4nm and 4.2nm silicon dioxide. When the sputtering power of Ta and Mo were 100W and 70W, respectively, the suitable work function for NMOS gate electrode, 4.2eV, could obtain. To prove interface thermal stability of thin film gate dielectric and Ta-Mo alloy, rapid thermal annealing was performed at $600^{\circ}C$ and $700^{\circ}C$ for 10sec in Ar ambient. The results of interface reaction were surveyed by change of silicon dioxide thickness and work function after annealing process. Also, the reliability of alloy gate and gate dielectric could be confirmed by quantity of leakage current. Ta-Mo alloy was showed low sheet resistance and thermal stability, namely, little change of gate dielectric and work function, after $700^{\circ}C$ annealing process.

• 전자공학회논문지
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• 제52권4호
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• pp.88-95
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• 2015

본 논문에서는 부성저항을 생성하는 회로로 알려진 RFNR 회로에 대한 새로운 분석을 소개한다. 새로운 분석에서는 RFNR 회로에 대한 수식분석의 정확성을 높이기 위해 트랜지스터의 게이트 저항과 소스 커패시턴스에 의한 영향을 고려하였다. 기존의 분석에서는 트랜지스터의 소스를 통하여 수식을 분석하였지만 제안된 수식에서는 회로의 공진부인 트랜지스터의 게이트를 통하여 회로를 분석했다. 그 결과, 제안하는 분석은 고주파수에서 기존의 분석보다 정확도를 향상시킬 수 있었다. 본 논문에서는 시뮬레이션을 통해 고주파수에서 분석의 정확도를 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.204-209
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• 2017

We have investigated a Mo/Au gate scheme for use in AlGaN/GaN-on-Si HFETs. AlGaN/GaN-on-Si HFETs were fabricated with Ni/Au or Mo/Au gates and their electrical characteristics were compared after thermal stress tests. While insignificant difference was observed in DC characteristics, the Mo/Au gate device exhibited lower on-resistance with superior pulsed characteristics in comparison with the Ni/Au gate device.