• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.50-55
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• 2016

In this paper, we have analyzed the electrical characteristics of 1200V trench gate field stop IGBT and have compared to NPT planar type IGBT and NPT planar field stop IGBT. As a result of analyzing, we obtained superior electrical characteristics of trench gate field stop IGBT than conventional IGBT. To begin with, the breakdown voltage characteristic was showed 1,460 V and on state voltage drop was showed 0.7 V. We obtained 3.5 V threshold voltage, too. To use these results, we have extracted optimal design and process parameter and designed trench gate field stop IGBT. The designed trench gate IGBT will use to inverter of renewable energy and automotive industry.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1966-1968
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• 1998

This paper describes a gate drive circuit for series connected IGBTs in high voltage applications. The proposed control criterion of the gate circuit is to actively limit the voltages during switching transients, while minimizing switching transient and losses. In order to achieve the control criterion, an analog closed loop control scheme is adopted. The performance of gate drive circuit is examined experimentally by the series connection of three IGBTs with conventional snubber circuits. The experimental results show the voltage balancing by an active control under wide variation in loads and imbalance conditions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Journal of Power Electronics
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• v.14 no.2
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• Journal of IKEEE
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• v.27 no.3
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• pp.308-312
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• 2023

The gate current sensing structure was proposed to more effectively control the regulation of the output voltage when the LDO regulator occurs in an overshoot or undershoot situation. In a typical existing LDO regulator, the regulation voltage changes when the load current changes. However, the operation speed of the pass transistor can be further improved by supplying/discharging the gate terminal current in the pass transistor using a gate current sensing structure. The input voltage of the LDO regulator using the gate current sensing structure is 3.3 V to 4.5 V, the output voltage is 3 V, and the load current has a maximum value of 250 mA. As a result of the simulation, a voltage change value of about 12 mV was confirmed when the load current changed up to 250 mA.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1292-1294
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• 2007

In this report, the effects of chemical surface treatments of ITO gate electrodes of OTFTs have been studied by using acid and base solutions. As a result, it is observed that the threshold voltage of OTFTs could be influenced and modified by the surface treatments. The device with an ITO gate electrode surface-treated by a base solution shows the lowest threshold voltage of -7.66 V, while the threshold voltages are about -13.51 V and -15.3 V for the devices without a surface treatment and with the acid solution treatment, respectively. It is thought that the work function of ITO electrode surface might be affected by the surface treatments, thereby influencing the threshold voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.67-78
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• 1984

EAROM device is an n-channel MOS transistor with a control gate stack ed on the floating gate. On account of channel injection type, channel lengths are designed 4-8 $\mu$m and chinnel widths 5-14 $\mu$m. These devices which have fourstructures of different type control gate are designed by NMOS 5 $\mu$m design rule and fabricated by double polysilicon gate NMOS Process. Double ion implantation is applied to increase punchthrough voltage and gate-controlled channel breakdown voltage. The drain and gate voltage for programming was 13-17V and 20-25V, respectively. EPROM cell fabricated could be erased not by optical method but by electrical method. The result of charge retention test showed decrease in stored charges by 4% after 200 hours at 1$25^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.63-68
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• 2003

The DC and RF characteristics of $In_{0.5}Ga_{0.5}P/In_{0.22}Ga_{0.78}As/GaAs$ p-HEMTs with a gate oxide layer of various thicknesses ($50{\;}{\AA},{\;}300{\;}{\AA}$) were investigated and compared with those of a Schottky-gate p-HEMT without the gate oxide layer. A prominent improvement in the breakdown voltage characteristics were observed for a p-HEMT having a gate oxide layer, which was implemented by using a liquid phase oxidation technique. The on-state breakdown voltage of the p-HEMT having the oxide layer of $50{\;}{\AA}$was ~2.3 times greater than that of a Schottky-gate p-HEMT. However, the p-HEMT having the gate oxide layer of $300{\;}{\AA}$ suffered from a poor gate-control capability due to the drain induced barrier lowering (DIBL) resulting from the thick gate oxide inspite of the lower gate leakage current and the higher on-state breakdown voltage. The results for a primitive p-HEMT having the gate oxide layer without any optimization of the structure and the process indicate the potential of p-HEMT having the gate oxide layer for high-power applications.