• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.2
• /
• pp.212-216
• /
• 2004

In this paper, we have fabricated a triode field emitter using carbon nanotubes (CNTs) directly grown by thermal chemical vapor deposition(CVD) method as an electron omission source. Vertically aligned CNTs have been grown in the center of the gate hole, to the size of 1.5 ${\mu}{\textrm}{m}$ in diameter, with help of a sacrificial layer of a type generally used in metal tip process. By the method of tilling the substrate, we made CNTs emitters both with and without SiO$_2$layer, a sidewall protector, deposited on sidewall of gate. After that we researched the electrical characteristics about two types of emitters. In effect, a sidewall protector can enhance the electrical characteristics by suppressing the problem of short circuits between the gate and the CNTs. The leakage current of an emitter with a sidewall protector is approximately sevenfold lower than that of an emitter without it at a gate voltage of 100 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.3
• /
• pp.190-193
• /
• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• Journal of Korean Society of Transportation
• /
• v.28 no.1
• /
• pp.15-24
• /
• 2010

Until now, the location and the size of gate are designed by only experience and intuitive use judgement. However there are no studies that investigated how many people will be using each subway gate depending on the location of gates. Therefore, the purpose of this study is to develop a gate choice model of subway station. The most critical element of a gate choice in subway station is the location of pedestrian's destinations. In this study, the development of the regression model is constructed from data of land use characteristic of station vicinity and the number of bus route and the space structure of station vicinity(Depth concept by Space Syntax analysis and total road length of station vicinity) by using the real data of 30 subway station in Seoul. This study found that subway pedestrian flow are mainly determined by three factors; the total floor space of commercial buildings, Total Depth(space structure index of station vicinity), and the number of bus route. The verification of a proposed model is done by using the real gate pedestrian data of two subway station in Seoul; Gang-nam and Yang-jae. The additional study of how to define the gate impact area is analysed. Therefore, this study will provide the theoretical bases in decision of gate location and size when a new subway station is opened in future.

• Elastomers and Composites
• /
• v.38 no.4
• /
• pp.295-302
• /
• 2003

The amount of shrinkage of injection molded parts is different from operational conditions of injection molding such as injection temperature, injection pressure and mold temperature, and mold design such as gate size. It also varies depending on the presence of crystalline structure in resins. In this study, part shrinkage was investigated for various operational conditions and resins. Poly(butylene terephthalate) (PBT) for crystalline polymer, and polycarbonate (PC) and poly(methyl methacrylate) (PMMA) for amorphous polymers were used. Crystall me polymer showed higher part shrinkage by about three times than that of amorphous polymers. Part shrinkage increased as melt and molt temperatures increased, and injection pressure decreased. Part shrinkage decreased as gate size increased since the pressure delivery is mush easier for larger gate sizes. Part shrinkage at the position close to the gate was larger than that or the position far from gate. This phenomenon might be occur by difference of residual stress.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.10
• /
• pp.895-903
• /
• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.4
• /
• pp.719-724
• /
• 2003

In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model (QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll off characteristics for threshold voltage of MOSFET with decreasing channel length, we know $\alpha$ value must be nearly 1 in the generalized scaling.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.585-593
• /
• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.1
• /
• pp.6-11
• /
• 2005

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

• ETRI Journal
• /
• v.18 no.3
• /
• pp.171-179
• /
• 1996

Fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with wide head T-shaped gates were fabricated by dose split electron beam lithography (DSL). The dimensions of gate head and footprint were optimized by controlling the splitted pattern size, dose, and spaces of each pattern. We obtained stable T-shaped gate of $0.15{\mu}m$ gate length with $1.35{\mu}m-wide$ head. The maximum extrinsic transconductance was 560 mS/mm. The minimum noise figure measured at 18 GHz at $V_{ds}=2V andI_{ds}=17mA$ was 0.41 dB with associated gain of 8.19 dB. At 12 GHz, the minimum noise figure and an associated gain were 0.26 and 10.25 dB, respectively. These noise figures are the lowest values ever reported for GaAs-based HEMTs. These results are attributed to the extremely low gate resistance of wide head T-shaped gate having a ratio of the head to footprint dimensions larger than 9.

• Journal of architectural history
• /
• v.21 no.5
• /
• pp.69-82
• /
• 2012

This study is basically about four-guardian-statutes-building-gate in 17th Century. In the field of art-history, there are four-guardian-statutes made of clay in order that the statutes are so gigantic and grotesque enough to threaten all the devils. This purpose of this study is to make sure that the similar variation occurred at the four-guardian-statutes-building-gate in 17th century. The results of this study are as follows. First, only Da-Po style four-guardian-statutes-building-gates were built in famous four temples separately from 1612 until the Manchu war of 1636. And there are gigantic four-guardian-statutes made of clay in the building. Second, there are Chul-mok Ik-gong style buildings were built in 1660s at Bo-Rim-Sa and Neung-Ga-Sa. The buildings including four-guardian-statutes-building-gate of Song-gwang-sa built in 1636 probably are all similar to earlier Da-Po style four-guardian-statutes-building-gates in the viewpoint of structural type and size of building. Third, it began to build Ik-gong style four-guardian-statutes-building-gates in 1676 at Su-ta-sa.