• Title/Summary/Keyword: Gate Metal

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Simple Route to High-performance and Solution-processed ZnO Thin Film Transistors Using Alkali Metal Doping

  • Kim, Yeon-Sang;Park, Si-Yun;Kim, Gyeong-Jun;Im, Geon-Hui
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.187-187
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    • 2012
  • Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

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Fabrication of MISFET type hydrogen sensor for high Performance (고성능 MISFET형 수소센서의 제작과 특성)

  • Kang, K.H.;Park, K.Y.;Han, S.D.;Choi, S.Y.
    • Journal of Hydrogen and New Energy
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    • v.15 no.4
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    • pp.317-323
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    • 2004
  • We fabricated a MISFET using Pd/NiCr gate for the detecting of hydrogen gas in the air and investigated its electrical characteristics. To improve stability and high concenntration sensitivity and remove the blister generated by the penetration of hydrogen atoms Pd/NiCr catalyst gate metal are used as dual gate. To reduce the gate drift voltage caused by the inflow of hydrogen, the gate insulators of sensing and reference FFET were constructed with double insulation layers of silicon dioxide and silicon nitride. The hydrogen response of MISFET were amplified with the difference of gate voltages of both MISFET. To minimize the drift and the noise, we used a OP177 operational amplifier. The sensitivity of the Pd/NiCr gate MISFET was lower than that of Pd/Pt gate MISFET, but it showed good stability and ability to detect high concentration hydrogen up to 1000ppm.

Optimization of feed system of base mold for washing machine using CAE (사출성형 CAE를 이용한 세탁기용 Base 성형용 금형의 유동 시스템 최적화)

  • Yoo, Min-ji;Kim, Kyung-A;Han, Seong-Ryeol
    • Design & Manufacturing
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    • v.15 no.1
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    • pp.1-7
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    • 2021
  • The position of the gate is one of the important factors for optimal injection molding. This is because inappropriate gate positions cannot fill the cavity uniformly, which can lead to defects such as contraction. In this study, CAE was performed on hot runner injection molding of the washing machine base and plasticity was compared by changing gate position from existing gate position. A total of two alternatives have been applied to compare the plasticity of the washing machine base according to its optimal gate position. The gate position of the improved molds and the gate position of the current mold is analyzed by injection molding analysis. The results of the fill time, the pressure at V/P switchover, clamping force, and deflection were compared. In washing machine base injection molding, the deflection was reduced by about 3.76% in the improved mold 2. In improved mold 1, the fill time during injection molding was reduced by 3.32% to enable uniform charging, and the clamping force was reduced by 31.24%. We have confirmed that the position of the gate can change the charging pressure and the clamping force and affect the quality and cost savings of the molded product.

A Study on sub 0.1$\mu\textrm{m}$ ULSI Device Quality Using Novel Titanium Silicide Formation Process & STI (새로운 티타늅 실리사이드 형성공정과 STI를 이용한 서브 0,1$\mu\textrm{m}$ ULSI급 소자의 특성연구)

  • Eom, Geum-Yong;O, Hwan-Sul
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.1-7
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    • 2002
  • Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

A Study on Improvement and Degradation of Si/SiO2 Interface Property for Gate Oxide with TiN Metal Gate

  • Lee, Byung-Hyun;Kim, Yong-Il;Kim, Bong-Soo;Woo, Dong-Soo;Park, Yong-Jik;Park, Dong-Gun;Lee, Si-Hyung;Rho, Yong-Han
    • Transactions on Electrical and Electronic Materials
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    • v.9 no.1
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    • pp.6-11
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    • 2008
  • In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

Implementation of Logic Gates Using Organic Thin Film Transistor for Gate Driver of Flexible Organic Light-Emitting Diode Displays (유기 박막 트랜지스터를 이용한 유연한 디스플레이의 게이트 드라이버용 로직 게이트 구현)

  • Cho, Seung-Il;Mizukami, Makoto
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.1
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    • pp.87-96
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    • 2019
  • Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

5-MeV Proton-irradiation characteristics of AlGaN/GaN - on-Si HEMTs with various Schottky metal gates

  • Cho, Heehyeong;Kim, Hyungtak
    • Journal of IKEEE
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    • v.22 no.2
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    • pp.484-487
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    • 2018
  • 5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

Properties of CNT field effect transistors using top gate electrodes (탑 게이트 탄소나노튜브 트랜지스터 특성 연구)

  • Park, Yong-Wook;Yoon, Seok-Jin
    • Journal of Sensor Science and Technology
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    • v.16 no.4
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    • pp.313-318
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    • 2007
  • Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

Gate-tunable Supercurrent in Graphene-based Josephson Junction (그래핀 조셉슨 접합에서 초전류의 게이트 전압 의존성)

  • Jeong, D.;Lee, G.H.;Doh, Y.J.;Lee, H.J.
    • Progress in Superconductivity
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    • v.13 no.1
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    • pp.47-51
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    • 2011
  • Mono-atomic-layer graphene is an interesting system for studying the relativistic carrier transport arising from a linear energy-momentum dispersion relation. An easy control of the carrier density in graphene by applying an external gate field makes the system even more useful. In this study, we measured the Josephson current in a device consisting of mono-layer graphene sheet sandwiched between two closely spaced (~300 nm) aluminum superconducting electrodes. Gate dependence of the supercurrent in graphene Josephson junction follows the gate dependence of the normal-state conductance. The gate-tunable and relatively large supercurrent in a graphene Josephson junction would facilitate our understanding on the weak-link behavior in a superconducting-normal metal-superconducting (SNS) type Josephson junction.

A Study on Parameters for Design of IGBT (IGBT 설계 Parameter 연구)

  • Lho, Young-Hwan;Lee, Sang-Yong;Kim, Yoon-Ho
    • Proceedings of the KSR Conference
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    • 2009.05a
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    • pp.1943-1950
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    • 2009
  • The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

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