• 제목/요약/키워드: Gate Insulator

검색결과 380건 처리시간 0.033초

High performance of ZnO thin film transistors using $SiN_x$ and organic PVP gate dielectrics

  • Kim, Young-Woong;Park, In-Sung;Kim, Young-Bae;Choi, Duck-Kyun
    • 한국결정성장학회지
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    • 제17권5호
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    • pp.187-191
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    • 2007
  • The device performance of ZnO-thin film transistors(ZnO-TFTs) with gate dielectrics of $SiO_2,\;SiN_x$ and Polyvinylphenol(PVP) having a bottom gate configuration were investigated. ZnO-TFTs can induce high device performance with low intrinsic carrier concentration of ZnO only by controlling gas flow rates without additional doping or annealing processes. The field effect mobility and on/off ratio of ZnO-TFTs with $SiN_x$ were $20.2cm^2V^{-1}s^{-1}\;and\;5{\times}10^6$ respectively which is higher than those previously reported. The device adoptable values of the mobility of $1.37cm^2V^{-1}s^{-1}$ and the on/off ratio of $6{\times}10^3$ were evaluated from the device with organic PVP dielectric.

Al/$BaTa_2O_6$/GaN MIS 구조의 특성 (Characteristics of Al/$BaTa_2O_6$/GaN MIS structure)

  • 김동식
    • 전자공학회논문지 IE
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    • 제43권2호
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    • pp.7-10
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    • 2006
  • 일반적인 산화 절연 게이트 대신 $BaTa_2O_6$를 사용한 GaN metal-insulator-semiconductor(MIS) 구조를 제작하였다. $Al_2O_3$(0001) 기판 위에서와 GaAs(001) 기판 위에서의 GaN 막의 누설 전류는 각각 $10^{-12}-10^{-13}A/cm^2$$10^{-6}-10^{-7}A/cm^2$로 측정되었다. 이 막의 누설전류는 각각 $Al_2O_3$(0001) 기판 위의 GaN인 경우는 45 MV/cm가 넘는 공간전하 제한전류에 의하여, GaAs(001) 기판 위의 GaN인 경우는 Poole-Frenkel 방출에 따른다는 것을 확인하였다.

이산화탄소를 이용한 ZTO 박막의 이동도와 안정성분석 (Element Analysis related to Mobility and Stability of ZTO Thin Film using the CO2 Gases)

  • 오데레사
    • 한국재료학회지
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    • 제28권12호
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    • pp.758-762
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    • 2018
  • The transfer characteristics of zinc tin oxide(ZTO) on silicon dioxide($SiO_2$) thin film transistor generally depend on the electrical properties of gate insulators. $SiO_2$ thin films are prepared with argon gas flow rates of 25 sccm and 30 sccm. The rate of ionization of $SiO_2$(25 sccm) decreases more than that of $SiO_2$(30 sccm), and then the generation of electrons decreases and the conductivity of $SiO_2$(25 sccm) is low. Relatively, the conductivity of $SiO_2$(30 sccm) increases because of the high rate of ionization of argon gases. Therefore, the insulating performance of $SiO_2$(25 sccm) is superior to that of $SiO_2$(30 sccm) because of the high potential barrier of $SiO_2$(25 sccm). The $ZTO/SiO_2$ transistors are prepared to research the $CO_2$ gas sensitivity. The stability of the transistor of $ZTO/SiO_2$(25 sccm) as a high insulator is superior owing to the high potential barrier. It is confirmed that the electrical properties of the insulator in transistor devices is an important factor to detect gases.

CdSe TFT의 제조 및 전기적 특성 (Fabrication and Characteristics of CdSe TFT)

  • 김기원;이우일
    • 대한전자공학회논문지
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    • 제18권4호
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    • pp.43-48
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    • 1981
  • CdSe 반수체와 SiO유전체를 사용하여 진공증착방법으로 박막트랜지스터를 제조하고 반도체의 두께 및 드레인-소오스간의 채널길이 변화가 박막트랜지스터의 특성에 미치는 경향을 조사하였다. 반도체의 두께를 1500Å으로 하고 채널길이를 40μm으로 제조한 TFT가 가장 좋은 특성을 나타내었다. 이 특성을 MOSFET의 관계식에 적용하여 이로부터 Cd Se반도체의 캐리어 이동도는 115㎠/V·sec였고 활성화 에너지는 0.13ev였다.

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Si-strained layer를 가지는 Silicon-Germanium on Insulator MOSFET에서의 이동도 개선 효과 (Improvement of carrier mobility on Silicon-Germanium on Insulator MOSFEI devices with a Si-strained layer)

  • 조원주;구현모;이우현;구상모;정홍배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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    • pp.7-8
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    • 2006
  • The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

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Optimization of H-IPS Structure for High Aperture Ratio.

  • Lee, Do-Young;Kim, Do-Sung;Kang, Byung-Goo;Kim, Eui-Tae;Kim, Bo-Ram;Kim, Jung-Han;Lim, Byung-Ho;Ahn, Byung-Chul
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.290-293
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    • 2006
  • We designed the H-IPS that has similar aperture ratio to the AS-IPS with organic insulator. To improve the aperture ratio without organic insulator, we positioned the pixel electrode over the preceding gate on the base of the H-IPS structure, and minimized the width of pixel and common electrodes. Without the additional process, we could obtain the similar brightness with that of AS-IPS in 15inch SXGA+ Panel.

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Pentacene OTFTs with $Al_2O_3$ gate insulator by Atomic Layer Deposition Process

  • Jin, Sung-Hun;Kim, Jin-Wook;Lee, Cheon-An;Park, Byung-Gook;Lee, Jong-Duk
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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    • pp.15-18
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    • 2003
  • Pentacene OTFTs of $Al_2O_3$ insulator treated with a diluted PMMA were fabricated for the application of the low voltage operation and large area displays. The operation voltage of 15 V and the mobility of 0.35 $cm^2/Vsec$ are obtained even adopting the thick dielectric of 100 nm which was deposited by atomic layer deposition at the temperature of $150^{\circ}C$. The current on-off ratio was $4.1{\times}10^4$ for the OTFTs treated with 9:1 PMMA and good saturation characteristics were obtained as drain voltage increases.

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ESD 보호를 위한 SOI 구조에서의 SCR의 제작 및 그 전기적 특성 분석 (Design and Analysis of SCR on the SOI structure for ESD Protection)

  • 배영석;천대환;권오성;성만영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.10-10
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    • 2010
  • ESD (Electrostatic Discharge) phenomenon occurs in everywhere and especially it damages to semiconductor devices. For ESD protection, there are some devices such as diode, GGNMOS (Gate-Grounded NMOS), SCR (Silicon-Controlled Rectifier), etc. Among them, diode and GGNMOS are usually chosen because of their small size, even though SCR has greater current capability than GGNMOS. In this paper, a novel SCR is proposed on the SOI (Silicon-On-Insulator) structure which has $1{\mu}m$ film thickness. In order to design and confirm the proposed SCR, TSUPREM4 and MEDICI simulators are used, respectively. According to the simulation result, although the proposed SCR has more compact size, it's electrical performance is better than electrical characteristics of conventional GGNMOS.

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AIN 버퍼층을 사용한 MFIS 구조의 제작 및 특성 (Fabrications and properties of MFIS structure using AIN buffer layer)

  • 정순원;김용성;이남열;김진규;정상현;김광호;유병곤;이원재;유인규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.29-32
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    • 2000
  • Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

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$LiNbO_3/Si_3N_4$ 구조를 이용한 MFIS 구조의 형성 및 특성 (Formations and properties of MFIS structure using $LiNbO_3/Si_3N_4$ structure)

  • 김용성;정상현;정순원;이남열;김진규;김광호;유병곤;이원재;유인규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.221-224
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    • 2000
  • We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

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