• 제목/요약/키워드: Gate Insulator

검색결과 380건 처리시간 0.028초

Latch up 전후의 SOI(SOS) LIGBT 구조에서의 열전도 특성 분석 (The thermal conductivity analysis of the SOI/SOS LIGBT structure)

  • 김제윤;김재욱;성만영
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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    • pp.79-82
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    • 2003
  • The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2$ and $Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability.

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$Si/Al_2O_3/Si$ 형태의 SOI(SOS) LIGBT 구조에서의 열전도 특성 분석 (The thermal conductivity analysis of the SOI LIGBT structure using $Al_2O_3$)

  • 김제윤;김재욱;성만영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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    • pp.163-166
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    • 2003
  • The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

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게이트절연막의 열처리가 Zinc Tin Oxide 투명 박막트랜지스터의 특성에 미치는 영향 (Annealing Effects of Gate-insulator on the Properties of Zinc Tin Oxide Transparent Thin Film Transistors)

  • 마대영
    • 한국전기전자재료학회논문지
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    • 제28권6호
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    • pp.365-370
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    • 2015
  • Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated on oxidized $n^+$ Si wafers. The thickness of ~30 nm $Al_2O_3$ films were deposited on the oxidized Si wafers by atomic layer deposition, which acted as the gate insulators of ZTO TTFTs. The $Al_2O_3$ films were rapid-annealed at $400^{\circ}C$, $600^{\circ}C$, $800^{\circ}C$, and $1,000^{\circ}C$, respectively. Active layers of ZTO films were deposited on the $Al_2O_3/SiO_2$ coated $n^+$ Si wafers by rf magnetron sputtering. Mobility and threshold voltage were measured as a function of the rapid-annealing temperature. X-ray photoelectron spectroscopy (XPS) were carried out to observe the chemical bindings of $Al_2O_3$ films. The annealing effects of gate-insulator on the properties of TTFTs were analyzed based on the results of XPS.

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

  • Boukortt, Nour El Islam;Hadri, Baghdad;Caddemi, Alina;Crupi, Giovanni;Patane, Salvatore
    • Transactions on Electrical and Electronic Materials
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    • 제17권6호
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    • pp.329-334
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    • 2016
  • In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

Photoinitiator-free Photosensitive Polyimide Gate Insulator for Organic Thin Film Transistor

  • Pyo, Seung-Moon;Lee, Moo-Yeol;Jeon, Ji-Hyun;Son, Hyun-Sam;Yi, Mi-Hye
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.885-888
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    • 2004
  • We have prepared and investigated the properties of photoinitiator-free photosensitive polyimide gate insulatos for organic thin-film transistors (OTFTs). The precursor was prepared from a dianhydride, 3,3',4,4'-Benzophenone tetracarboxylic dianhydride (BTDA) and novel aromatic diamine, 7-(3,5-diaminobenzoyloxy) coumarine (DA-CM). Photo-patternability of the polyimide precursor film and surface morphology of the films before and after photo-patterning process were investigated and negative pattern with a resolution of 50 ${\mu}m$ was obtained nicely. In addition, we have fabricated OTFTs with pentacene and photosensitive polyimide as a semiconductor and a gate insulator; respectively. According to the device geometry, the ${\mu}$, current modulation ratio and subthreshold swing of the devices were around 0.2${\sim}$0.4 $cm^2$/Vs, more than $10^5$ and around 3${\sim}$5 V/dec, respectively.

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Decoupled Plasma Nitridation에 의한 Flicker 노이즈 개선에 관한 연구 (A study on Flicker Noise Improvement by Decoupled Plasma Nitridation)

  • 문성열;강성준;정양희
    • 한국전자통신학회논문지
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    • 제9권7호
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    • pp.747-752
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    • 2014
  • 본 논문은 $0.13{\mu}m$ 기술의 디자인을 10% 축소하는데 기존의 로직 디바이스만의 축소와는 달리 로직뿐 아니라 입, 출력 회로의 축소에 관한 것이다. 게이트 산화막(1.2V)을 decoupled plasma nitridation(DPN) oxide로 변경함으로써 flicker 노이즈를 축소 전 공정에 비해 1/3-1/5배 감소됨을 확인하였다. 또한, 축소에 의한 피할 수 없는 문제는 일반적인 metal insulator metal(MIM)의 캐패시터 문제이다. 이를 해결하기 위하여 20% 높은 MIM 캐패시터($1.2fF/{\mu}m^2$)를 개선하고 그 특성을 평가하였다.

Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs

  • Park, In Jun;Shin, Changhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권5호
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    • pp.511-515
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    • 2013
  • A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).