• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.482-485
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• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.379-382
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• 2004

In this paper we fabricated a test panel for AMOLED on glass and PET substrate. The test panel consisted of the various size of OTFTs and OLEDs and the current driving capability of OTFTs for OLEDs has been investigated. OTFTs were made of the inverted staggered structure and employed polyvinylphenol (PVP) as the gate insulator and pentacene thin film as the active layer. The OTFTs produced the filed effect mobility of $0.3 cm^2/V.sec$ and on/off current ratio of $10^5$. OLEDs consisted of TPD for HTL and Alq3 for EML with 35nm thick, generating green monochrome light. We found that OTFT with channel length of 70${\mu}m$ and channel width of over 3.5mm provided the sufficient current to OLED to generate the luminescence of $0.3Cd/m^2$.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1034-1037
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• 2004

In this paper we fabricated a test panel for AMOLED on glass and PET substrate. The test panel consisted of the various size of OTFTs and OLEDs and the current driving capability of OTFTs for OLEDs has been investigated. OTFTs were made of the inverted staggered structure and employed polyvinylphenol (PVP) as the gate insulator and pentacene thin film as the active layer. The OTFTs produced the filed effect mobility of 0.3$cm^2$/V.sec and on/off current ratio of $10^5$. OLEDs consisted of TPD for HTL and Alq3 for EML with 35nm thick, generating green monochrome light. We found that OTFT with channel length of 70${\mu}m$and channel width of over 3.5mm provided the sufficient current to OLED to generate the luminescence of 0.3Cd/$m^2$.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1284-1287
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• 2007

Titanium dioxide ($TiO_2$) is promising candidate for fabricating blocking layer of gate dielectrics in non-volatile memory (NVM). In this work, we investigated $TiO_2$ as high dielectric constant material instead of silicon dioxide ($SiO_2$), which is generally used as blocking layer for NVM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.70-73
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• 2001

MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.81-82
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• 2006

SOI(Silicon-On-Insulator) MOSFET의 전기적 특성에 미치는 게이트 산화막과 계면준위 밀도의 관계를 조사하였다. 결함이 발생하지 않는 얕은 소스/드레인 접합을 형성하기 위하여 급속열처리를 이용한 고상확산방법으로 제작한 SOI MOSFET 소자는 급속열처리 과정에서 계면준위가 증가하여 소자의 특성이 열화된다. 이를 개선하기 위하여 $H_2/N_2$ 분위기에서 후속 열처리 공정을 함으로써 소자의 특성이 향상됨을 볼 수 있었다. 이와같이 급속열처리 공정과 $H_2/H_2$ 분위기에서의 후속 열처리 공정이 소자 특성에 미치는 영향을 분석하기 위하여 소자 시뮬레이션을 이용하여 게이트 산화막과 채널 사이의 계면준위 밀도를 분석하였다. 그 결과, n-MOSFET의 경우에는 acceptor-type trap, p-MOSFET의 경우에는 donor-type trap density가 소자특성에 큰 영향을 미치는 것을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.309-313
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• 2006

We demonstrated 2.2inch qqVGA AMOLED display drived by ultra low temperature poly-Si (ULTPS) TFT not transferred but direct fabricated below $200^{\circ}C$. Si channel was crystallized by decreasing impurity concentration even at room temperature. Gate insulator with a breakdown field exceeding 8 MV/cm was realized by Inductively coupled plasma - CVD. In order to reduce stress of plastic, organic film was coated as inter-dielectric and passivation layers. Finally, ULTPS TFT of which mobility is over $20cm^2/Vsec$ was fabricated on transparent plastic substrate and drived OLED display successfully.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1701-1703
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• 2006

Here we describe a novel driving scheme in the form of negative AC bias stress (NAC) to compensate shift in the threshold voltage for hydrogenated amorphous silicon (${\alpha}$-Si:H) thin film transistor (TFT) for AMOLED applications. This scheme preserves the threshold voltage shift of ${\alpha}$-Si:H TFT for infinitely long duration of time(>30,000 hours) and thereby overall performance, without using any additional TFTs for compensation. We briefly describe about the possible driving schemes in order to implement for real time AMOLED applications. We attribute most of the results based on concept of plugging holes and electrons across the interface of the gate insulator in a controlled manner.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.