• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.79-82
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2$ and $Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.71-71
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.275.2-275.2
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.269.1-269.1
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• 2009

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.365-370
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• 2015

Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated on oxidized $n^+$ Si wafers. The thickness of ~30 nm $Al_2O_3$ films were deposited on the oxidized Si wafers by atomic layer deposition, which acted as the gate insulators of ZTO TTFTs. The $Al_2O_3$ films were rapid-annealed at $400^{\circ}C$, $600^{\circ}C$, $800^{\circ}C$, and $1,000^{\circ}C$, respectively. Active layers of ZTO films were deposited on the $Al_2O_3/SiO_2$ coated $n^+$ Si wafers by rf magnetron sputtering. Mobility and threshold voltage were measured as a function of the rapid-annealing temperature. X-ray photoelectron spectroscopy (XPS) were carried out to observe the chemical bindings of $Al_2O_3$ films. The annealing effects of gate-insulator on the properties of TTFTs were analyzed based on the results of XPS.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.885-888
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• 2004

We have prepared and investigated the properties of photoinitiator-free photosensitive polyimide gate insulatos for organic thin-film transistors (OTFTs). The precursor was prepared from a dianhydride, 3,3',4,4'-Benzophenone tetracarboxylic dianhydride (BTDA) and novel aromatic diamine, 7-(3,5-diaminobenzoyloxy) coumarine (DA-CM). Photo-patternability of the polyimide precursor film and surface morphology of the films before and after photo-patterning process were investigated and negative pattern with a resolution of 50 ${\mu}m$ was obtained nicely. In addition, we have fabricated OTFTs with pentacene and photosensitive polyimide as a semiconductor and a gate insulator; respectively. According to the device geometry, the ${\mu}$, current modulation ratio and subthreshold swing of the devices were around 0.2${\sim}$0.4 $cm^2$/Vs, more than $10^5$ and around 3${\sim}$5 V/dec, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.747-752
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).