• Journal of IKEEE
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• v.21 no.2
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• pp.170-173
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• 2017

In this study, we fabricate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with three different gate electrode materials of Al, Mo and Pt on plastic substrates and investigate their electrical characteristics. Compared to an a-IGZO TFT with Al gate electrode, the threshold voltage of an a-IGZO TFT with a Pt electrode decreases from -4.2 to -0.3 V. and the filed-effect mobility is improved from 15.8 to $22.1cm^2/V{\cdot}s$. The threshold voltage shift of the TFT is affected by the difference between the work function of the gate electrode and the Fermi energy of the channel layer. Moreover, the Pt gate electrode is considered to be the suitable material in terms of the electrical characteristics of the TFT. In addition, an description on an a-IGZO TFT with a Mo electrode will be given here.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.77-82
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• 1996

The breakdown characteristics of metal-oxide-semiconductor(MOS) capacitors fabricated by Al, polysilicon, and tungsten polycide gate electrodes onto gate oxide was evaluated by time zero dielectric breakdwon (TZDB). The average breakdown field of the gate oxide with tungsten polycide electride was lower than that of the polysilicon electrode. The B model (1~8MV/cm) failure of the gate oxide with tungsten polycide electrode was increased with increasing annealing temperature in the dry $O_{2}$ ambient. This is attributed ot fluorine and tungsten diffusion from thungsten silicide film into the gate oxide, and stress increase of tungsten polcide after annealing treatment.

• Polymer(Korea)
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• v.35 no.4
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• pp.370-374
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• 2011

A conductive PANI solution was successfully fabricated by doping with camphorsulfonic acid and the polymerization of aniline and the confirmation of doping were characterized by FTIR spectroscopy. In organic thin film transistors, PANI gate electrodes were spin-coated on a PES substrate and their conductivity variations were monitored by a 4-probe method with different annealing temperatures. The surface properties of PANI thin films were investigated by an AFM and an optical microscope, OTFTs with PANI gate electrode had characteristics of carrier mobility as large as 0.15 $cm^2$/Vs and on/off ratio of $2.4{\times}10^6$, Au gate OTFTs with the same configuration were fabricated to investigate the effect of polymer gate electrode for the comparison of device performances. We could obtain the comparable performances of PANI devices to those of Au gate devices, resulting in an excellent alternative as an electrode in flexible OTFTs instead of an expensive Au electrode.

• Progress in Superconductivity
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• v.3 no.1
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• pp.74-77
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• 2001

We have fabricated a high-Tc superconductive transistor with polyvinylidene fluoride (PVDF) gate electrode on MgO bicrystal Josephson junction by spin-coating method. The PVDF ferroelectric film is found to be suitable fur a gate electrode of the superconductive transistor since it has not only small leakage current but also high dieletric constant at low temperature. For the application of superconducting-FET, we investigated millimeter wave properties (60 GHz band) of the Josephson junction with PVDF gate electrode.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.4
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• pp.22-27
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• 2004

The gas discharge AND gate which have been newly proposed is applied to three electrode surface discharge AC PDP. The address discharge characteristics by the DC-AC floating discharge by which Y electrode is made floating electrode is analyzed The address discharge can be begun by using the floating discharge from the experiment result Moreover, the display discharge can be sustained. The DC priming discharge that the floating discharge is matched to timing is generated in a supplementary electrode. As a result, space charge is supplied enough to the space of the floating discharge and the data voltage is lowered up to l00(V). Driving method to use this DC-AC floating discharge is able to obtain the address operation margin of l00(V).

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2001.11a
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• pp.39-46
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• 2001

The plasma display panel with the electrode structure of new discharge AND gate was developed and the driving system for experiment was developed. And discharge AND gate operation was verified. Discharge AND gate operated by the operation speed of 8$mutextrm{s}$ and the operation margin of 20V. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because this method uses the DC discharge, the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the imput discharge and the output discharge of AND gate are separate, the display discharge can be prevented from passing AND gate. Therefore, it is possible to apply to the large screen plasma display. And the decrease of contrast ratio does not occur because the scanning electrical discharge does not influence the picture quality.

• Applied Chemistry for Engineering
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• v.20 no.1
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• pp.99-103
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• 2009

HBr and $O_2$ in $Cl_2$ gas ambient for the high density plasma gate etching has been used to increase the performance of gate electrode in semiconductor devices. When an un-doped amorphous silicon layer was used for a gate electrode material, the notching profile was observed at the outer sidewall foot of the outermost line. This phenomenon can be explained by the electron shading effect: i.e., electrons are captured at the photoresist sidewall while ions pass through the photoresist sidewall and reach the oxide surface at a narrowly spaced pattern during the over etch step. The potential distribution between gate lines deflects the ions trajectory toward the gate sidewall. In this study, an appropriate mechanism was proposed to explain the occurrence of notching in the gate electrode of un-doped amorphous silicon.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.