• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.693-695
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• 2003

In this paper, we have investigated temperature-dependent characteristics of current-voltage for double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated the temperature-dependent characteristics of current-voltage and drain voltage is changed from 0V to 5.0V at $V_{mg}$ =1.5V and $V_{sg}$ =3.0V. We have obtained a very good characteristics of current-voltage for 77K. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.182-192
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• 2003

A new Monte Carlo (MC) simulator for electron beam lithography process in the multi-layer resists and compound semiconductor substrates has been developed in order to fabricate and develop the high-speed PHEMT devices for millimeter-wave frequencies. For the accurate and efficient calculation of the transferred and deposited energy distribution to the multi-component and multi-layer targets by electron beams, we newly modeled for the multi-layer resists and heterogeneous multi-layer substrates. By this model, the T-shaped gate fabrication process by electron beam lithography in the PHEMT device has been simulated and analyzed. The simulation results are shown along with the SEM observations in the T-gate formation process, which verifies the new model in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.777-779
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• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.23-36
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• 2004

A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process has been developed for sub-0.l${\mu}{\textrm}{m}$ T-shaped gate formation in the HEMT devices for millimeter-wave frequencies. For the exposure process by electron to we newly and efficiently modeled the inner-shell electron scattering and its discrete energy loss with an incident electron for multi-layer resists and heterogeneous multi-layer targets in the MC simulation. In order to form the T-gate shape in resist layers, we usually use the different developer for each resist layer to obtain good reproducibility in the fabrication of HEMT devices. To model accurately the real fabrication process of electron beam lithography, we have applied the different developers in trilayer resist system By using this model we have simulated and analyzed 0.l${\mu}{\textrm}{m}$ T-gate fabrication process in the HEMT devices, and showed our simulation results with the SEM observations of the T-shaped gate process.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1309-1310
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• 2007

본 논문에서는 IGBT 소자 중 온저항을 낮추고 집적성을 향상시키기 위해 고안된 트렌치 게이트 IGBT의 단점인 게이트 코너에서의 전계 집중현상을 완화하기 위해 P+ 베이스 영역에 트렌치 전극을 형성하고, 트렌치 바닥면에 P+ 층을 형성한 새로운 구조를 제안하고 TSUPREM과 MEDICI 시뮬레이션을 사용하여 전기적 특성을 분석하였다. 제안한 구조를 시뮬레이션한 결과 순방향 저지시에 15% 이상의 항복전압 향상을 보였으며, 이 때 온저항 특성과 문턱전압의 변화는 없었다. 전계 분포를 3차원적 시뮬레이션을 통해 트렌치 전극 바닥에 형성된 P+ 층에 의해 전계집중이 분산되는 전계분산 효과에 의해 항복전압을 향상시킴을 확인하였다. 전계분산 효과에 의한 항복전압향상은 트렌치 게이트의 코너와 트렌치 전극의 코너의 깊이가 같을수록 두 코너 사이의 거리가 가까울수록 커짐을 시뮬레이션을 통해 확인하였다. 제안 구조는 공정상 복잡성이 야기되지만 15%이상의 항복전압향상 효과는 소자 특성 개선에서 많은 응용이 기대된다.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.141-143
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• 2002

We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.99-105
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• 1994

Most of the companies are forced to cut down the manufacturing cost to survive in the competitive environment. Among others, material distribution cost alone takes substantial portion of the total manufacturing cost. In this study, we investigate the waiting phenomenon in the toll gate and propose a new toll booth layout to reduce the waiting time, thereby reduce the total material distribution cost. SIMAN, a simulation language, is employed to evaluate the proposed layout. The experimental results show that the layout reduces the waiting time significantly. Furthermore, the result indicates that determination of the intermediate buffer space affects the performance of the proposed layout.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.