• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Journal of The Korean Society of Agricultural Engineers
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• v.54 no.3
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• pp.133-139
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• 2012

Dynamic characteristic of lift gate supported by plane truss is studied by a model test scaled with the ratio of 1 : 31.25 in the four major rivers project. The vibrations of gate supported by the plane truss is assessed in comparison with those of gate supported by the space truss which was tested formerly. The gate model is made of acryl panel and calibrated by lead. A model test is conducted under the different gate opening and upstream water levels conditions in the concrete test flume dimensioned 1.6 m in width, 0.8 m in height and 24 m in length. In order to verify the model, natural frequencies of the model gate are measured, and compared with the numerical results. The vibrations of gate model supported by the plane truss in opening height of 1.0 cm~2.0 cm shows greater than one supported by the space truss. It is found that the gate model supported by the plane truss is less desirable than one supported by the space truss. thus, the latter type of gate model is requested to design.

• Journal of Soil and Groundwater Environment
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• v.28 no.3
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• pp.1-11
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• 2023

Permeable reactive barrier (PRB) is a prominent in-situ remedial option for cleanup of contaminated groundwater and has been gaining increasing popularity in recent years. Funnel-and-gate systems, comprised of two side wings of impermeable walls and a central gate wall, are frequently implemented in many sites, but often suffers from bypassing of groundwater due to the progressive clogging of the gate wall over extended period of time. This study investigated technical feasibility of a hybrid funnel-and-gate system designed to address the flow deterioration in the gate wall. The key attribute of the proposed hybrid system is the operation of drainage units at the barrier walls and rear end of the gate wall. A conceptual modeling with MODFLOW indicated the groundwater inside the barrier was maintained at appropriate level to be guided toward the gate wall, yielding constant discharging of groundwater from the gate.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.31-35
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• 2020

This study demonstrates metal-oxide based memtransistor device and the gate tunable memristive characteristic using atomic layer deposition (ALD) and ZnO n-type oxide semiconductor. We fabricated a memtransistor device having channel width 70 ㎛, channel length 5 ㎛, back gate, using 40 nm thick ZnO thin film, and measured gate-tunable memristive characteristics at each gate voltage (50V, 30V, 10V, 0V, -10V, -30V, -50V) under humidity of 40%, 50%, 60%, and 70% respectively, in order to investigate the relation between a memristive characteristic and hydrogen doping effect on the ZnO memtransistor device. The electron mobility and gate controllability of memtransistor device decreased with an increase of humidity due to increased electron carrier concentration by hydrogen doping effect. The gate-tunable memristive characteristic was observed under humidity of 60% 70%. Resistive switching ratio increased with an increase of humidity while it loses gate controllability. Consequently, we could obtain both gate controllability and the large resistive switching ratio under humidity of 60%.

• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.327-332
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• 1996

In this study, the effects of $WSi_x$, thickness and fluorine concentration in tungsten polycide gate structure on gate oxide were investigated. As $WSi_x$, thickness increases, gate oxide thickness increases with fluorine incorporation in gate oxide, and time-to-breakdown($T_{BD,50%}$) of oxide decreases. The stress change with $WSi_x$ thickness was also examined. But it is understood that the dominant factor to degrade gate oxide properties is not the stress but the fluorine, incorporated during $WSi_x$ deposition, diffused into $WSiO_2$ after heat treatment. In order to understand the effect of fluorine diffusion into oxidem fluorine ion implanted gates were compared. The thickness variation and $T_{BD,50%}$ of gate oxide is saturated over 600 $\AA$ thickness of $WSi_x$. The TEM and SIMS studies show the microstructure less than 600 $\AA$ thickness is dense and flat in surface. However, over 600$\AA$, the microstructure of $WSi_x$ is divided into two parts: upper porous phase with rugged surface and lower dense phase with smmoth interface. And this upper phase is transformed into oxygen rich crystalline phase after annealing, and the fluorine is captured in this layer. Therefore, the fluorine diffusion into the gate oxide is saturated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.1
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• pp.13-19
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• 2002

The plasma display panel with the electrode structure of new discharge AND gate was proposed and the driving system for experiment was developed. And discharge AND gate operation was verified. Discharge AND gate operated by the operation speed of 8${\mu}\textrm{s}$ and the operation margin of 20V. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because this method uses the DC discharge, the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the input discharge and the output discharge of AND gate are separate, the display discharge can be prevented from passing AND gate. Therefore it is possible to app1y to the large screen plasma display. And the decrease of contrast ratio does not occur because the scanning discharge does not influence the picture quality.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1266-1272
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• 2012

An InGaZnO thin film transistor with different gate lengths and widths have been fabricated and their device degradations with device sizes have been also performed after negative gate bias stress. The threshold voltage and subthreshold swing have been decreased with decrease of gate length. However, the threshold voltages were increased with the decrease of gate lengths. The transfer curves were negatively shifted after negative gate stress and the threshold voltage was decreased. However, the subthreshold swing was not changed after negative gate stress. This is due to the hole trapping in the gate dielectric materials. The decreases of the threshold voltage variation with the decrease of gate length and the increase of gate width were believed due to the less hole injection into gate dielectrics after a negative gate stress.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.458-466
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• 2012

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.