• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.05a
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• pp.52-54
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• 1993

A new type of semiconductor fuse-link with fuse elements deposited on ceramic substrate introduced. The construction and aging property of this fuse-link, as well as the test circuitry built especially for the development of this fuse-link explained below.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.3
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• pp.129-136
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• 2020

A Cut Out Switch (COS) is used for line protection and pole transformer protection in power systems. The COS used to protect the pole transformer is installed on the power side of the pole transformer to protect the electric equipment from fault currents. The COS is composed largely of a body and a fuse holder, and when the fault current is energized, the element of the fuse link in the fuse holder is melted to block the fault current. The arc generated when the COS fuse link is blown causes fire and noise, causing discomfort to residents in the surrounding area, and the arc flame can cause secondary damage to the peripheral device. In this study, a current-limiting COS fuse with improved overcurrent blocking performance rather than explosion type was developed to solve the arc and noise problems during COS operation. The overcurrent breaking performance of the current-limiting COS improves the reliability by developing a striker and COS fuse bracket. In addition, this study aimed to verify the performance of the developed current-limiting COS fuse through a test at an authorized institution.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.644-650
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• 2018

According to a miniaturization and integration of electric device, a little size of fuse satisfying the current carrying capacity as well as an explosive tolerance and current interrupt rating are required. Fe-Ni alloy is applied to decrease an oxidation of fuse elements. A resistance and T.C.R(temperature coefficient of resistance) of a fuse are analyzed by changing a content of Ni And full rated current I-T curve from 1A to 6.3A has been tested. In order to an explosive energy, a straight wire type is selected to reduce a fuse melting time. An interrupt rating test was conducted by changing a content of Ni and the optimal content of Ni is to be 40%.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.3
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• pp.131-137
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• 2017

In order to safely protect high over current flowing into the main circuit at short-circuit without any explosion or fire, the enclosed cartridge fuse with a high interrupting capacity should be applied. But this fuse is impossible to be applied to an inner electronic circuit because of a limited space problem result from the miniaturization trend of products. Therefore, it is necessary to apply a sub-miniature fuse with a relatively small size. However the semi-enclosed fuse which is more free for an influx of air than the enclosed cartridge fuse and is possible to protect fuse elements with chemical and physical combination can be adoptable. But it has a limit of implementing the characteristic of a high breaking capacity. For these reasons, the Fe-42wt％Ni fuse elements alloy and fuse-link with less space were designed to increase a breaking capacity of sub-miniature fuse and its safety for fire and explosion was confirmed in this paper.

• Journal of Power Electronics
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• v.2 no.2
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• pp.88-94
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• 2002

The demand for protection of power electronic application has during the last couple of vears increased regarding the high-power IGBT modules. Even with an active protection, a high power IGBT still has a risk of exhibiting a violent rupture in the case of a fault if IGBT Fuses do not protect it. By introducing fuses into the circuit this will increase the circuit inductance and slight inductance over-voltage during the turn-off of the diode and the IGBT. It is therefore vital when using fuses that the added inductance is kept at a minimum. This paper discuss three issues regarding the IGBT Fuse protection of adding inductance of existing High-speed and new Typower Fuse protection. First, the problem of adding inductance of exiting High-speed and new Typower Fuse DC-link circuit is treated, second a short discussion of protection of the IGBT module is done, and finally, the impect of the high frwquency loading on the currying capability of the fuses is presented.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.