• Proceedings of the KWS Conference
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• 2006.05a
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• Journal of the Korean institute of surface engineering
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• v.28 no.2
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.62-67
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• 2010

Our research group has investigated that RFID tag packaging development and RFID tag flip chip bonding method influences on the industry-environmental customized RFID tag development that has applications to various industry environmental conditions. RFID tag flip chip bonding is consisting with wire bonding, ultrasonic bonding, heat plate bonding, and laser bonding and those methods are also depending on the different RFID tag development. Our research data shows that, among the various industrial environments such as an extremely high temperature, cryogenic, high-humidity, flexible, high-durable, development of RFID tag in an extremely high temperature is inappropriate for laser bonding method, converting of heat energy as absorbing light energy or heat plate bonding method of straight heat transferring manner, on the other hand, is suitable for wire bonding method which directly connect bump to pattern using wire.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Transactions of the Korean Society of Machine Tool Engineers
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• v.18 no.1
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• pp.116-121
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• 2009

Thermosonic flip chip bonding is an important technology for the electronic packaging due to its simplicity, cost effectiveness and clean and dry process. Mechanical properties of the horn and the shank, such as the natural frequency and the amplitude, have a great effect on the bonding capability of the transverse flip chip bonding system. In this research, two kinds of study are performed. The first is the new design of the clamp and the second is the effect of tolerance parameters to the performance of the system. The clamp with a bent shape is newly designed to hold the nodal point of the flip chip. The second is the effect of the design parameters on the vibration amplitude and planarity at the end of the shank. The variation of the tolerance parameters changes the amplitude and the frequency of the vibration of the shank. They, in turn, have an effect on the quantity of the plastic deformation of the gold ball bump, which determined the quality of the flip chip bonding. The tolerance parameters that give the great effect on the amplitude of the shank are determined using Taguchi's method. Error of set-up angle, the length and diameter of horn and error of the length of the shank are determined to be the parameters that have peat effect on the amplitude of the system.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.140-151
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• 1996

In this paper, we analyze the variations of thermal characteristics of LD (laser diode) arrays packaged by a flip-chip bonding method. When we simulate the temperature distribution in LD arrays with a BEM (boundary element method) program coded in this paper, we find that thermal crosstalks in LD arrays packaged by the flip-chip bonding method increases by 250-340% compared to that in LD arrays packaged by previous methods. In the LD array module packaged by the flip-chip bonding technique without TEC (thermo-electric cooler), the important parameter is the absolute temperature of the active layer increased due cooler), the important parameter is the absolute temperature of th eactiv elayers of LD arrays to thermal crosstalk. And we find that the temperature of the active layers of LD arrays increases up to 125$^{\circ}C$ whenall four LDs, without a carefully designed heatsink, are turned on, assuming the power consumption of 100mW from each LD. In order to reduce thermal crosstalk we propose a heatsink sturcture which can decrease the temeprature at the active layer by 40%.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.9-17
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• 2008

Cu mushroom bumps were formed by electrodeposition and flip-chip bonded to Sn substrate pads. Contact resistances of the Cu-mushroom-bump joints were measured and compared with those of the Sn-planar-bump joints. The Cu-mushroom-bump joints, processed at bonding stresses ranging from 19.1 to 95.2 MPa, exhibited contact resistances near $15m\Omega$/bump. Superior contact-resistance characteristics to those of the Sn-planar-bump joints were obtained with the Cu-mushroom-bump joints. Contact resistance of the Cu-mushroom-bump joints was not dependent upon the thickness of the as-elecroplated Sn-capcoating layer ranging from $1{\mu}m$ to $4{\mu}m$. When the Sn-cap-coating layer was reflowed, however, the contact resistance was greatly affected by the thickness and the reflow time of the Sn-cap-coating layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1005-1008
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• 2003

We report a new FCOG (flip chip on glass) technique using solder bumps for display packaging applications. The In and Sn solder bumps of 40 ${\mu}m$ pitches were formed on Si and glass substrate. The In and Sn bumps were bonded at 125 at the pressure of 3 mN/bump. The metallurgical bonding was confirmed using cross-sectional SEM. The contact resistance of the solder joint was 65 $m{\Omega}$ which was much lower than that of the joint made using the conventional ACF bonding technique. We demonstrate that the new COG technique using solder bump to bump direct bonding can be applied to advanced LCDs that lead to require higher quality, better resolution, and lower power consumption.