• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.114-121
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• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1005-1009
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• 2006

High quality three-dimensional (3D) heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate to improve the efficiency of tarrier transport. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources (As2, As4) were varied to calibrate the selective area growth conditions and the 3D GaAs-AlGaAs heterostructures were fabricated into the ridge type and the V-groove type. Scanning micro-photoluminescence $({\mu}-PL)$ measurements and the following analysis revealed that the gradually (adiabatically) coupled 1D-2DEG (electron gas) field effect transistor (FET) system was successfully realized. These 3D-heterostructures are expected to be useful for the realization of high-performance mesoscopic electronic devices and circuits since it makes it possible to form direct ohmic contact onto the (quasi) 1D electron channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.167-168
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• 2006

High quality 3D-heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources ($As_2$, $As_4$) were varied to calibrate the selective area growth conditions. Scanning micro-photoluminescence ($\mu$-PL) measurements and following analysis revealed that the gradually (adiabatically) coupled 2DEG-1D-1DEG field effect transistor (FET) system was realized. This 3D-heterostructure is very promising for the realization of the meso-scopic electronic devices and circuits since it makes it possible to form direct ohmic contact to the (quasi) 1DEG.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.180-187
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• 1997

We demonstrate the improvement of sensitivity and analysis of operating characteristics of the piezoelectric pressure sensor using ZnO piezoelectric thin film and FET(field effect transistor) for sensing applied pressure and transforming the pressure into electrical signals, respectively. The sensitivity of the PSFET(pressure sensitive field effect transistor) was improved by using highly-oriented ZnO film perpendicular to the substrate surface and the operating characteristics was investigated by monitoring output voltage with time in various static pressure levels.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.387.1-387.1
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• 2014

A new class of temperature-sensing materials is demonstrated along with their integration into transparent and flexible field-effect transistor (FET) temperature sensors with high thermal responsivity, stability, and reproducibility. The novelty of this particular type of temperature sensor is the incorporation of an R-GO/P(VDF-TrFE) nanocomposite channel as a sensing layer that is highly responsive to temperature, and is optically transparent and mechanically flexible. Furthermore, the nanocomposite sensing layer is easily coated onto flexible substrates for the fabrication of transparent and flexible FETs using a simple spin-coating method. The transparent and flexible nanocomposite FETs are capable of detecting an extremely small temperature change as small as $0.1^{\circ}C$ and are highly responsive to human body temperature. Temperature responsivity and optical transmittance of transparent nanocomposite FETs were adjustable and tuneable by changing the thickness and R-GO concentration of the nanocomposite.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• Journal of Sensor Science and Technology
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• v.21 no.5
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• pp.339-344
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• 2012

This article describes a novel method for the detection of amyloid-${\beta}$($A{\beta}$) peptide that utilizes a photo-sensitive field-effect transistor (p-FET). According to a recent study, $A{\beta}$ protein has been known to play a central role in the pathogenesis of Alzheimer's disease (AD). Accordingly, we investigated the variation of photo current generated from p-FET with and without intracellular magnetic beads conjugated with $A{\beta}$ peptides, which are placed on the p-FET sensing areas. The decrease of photo current was observed due to the presence of the magnetic beads on the channel region. Moreover, a similar characteristic was shown when the Raw 264 cells take in magnetic beads treated with $A{\beta}$ peptide. This means that it is possible to simply detect a certain protein using magnetic beads and a p-FET device. Therefore, in this paper, we suggest that our method could detect tiny amounts of $A{\beta}$ for early diagnosis of AD using the p-FET devices.

• Transactions on Electrical and Electronic Materials
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• v.8 no.4
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• pp.174-177
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• 2007

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine ($F_{16}CuPC$) and copper phthalocyanine (CuPc) as an active layer. And we observed the surface morphology of the $F_{16}CuPC$ thin film. The $F_{16}CuPC$ thin film thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. And we also fabricated the $F_{16}CuPc/CuPc$ double layer FET and with different $F_{16}CuPc$ film thickness devices. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility. From the double layer FET devices, we observed the higher drain current more than single layer FET devices.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.