• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.170-172
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• 2002

The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.

• 한국재료학회지
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• 제21권2호
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.21-26
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• 2005

The field effect transistors (FETs) were fabricated ell $Y_2O_3/Si(100)$ substrates by the conventional memory processes and sol-gel process using $(Bi,La)Ti_3O_{12}(BLT)$ ferroelectric gate materials. The remnant polarization ($2Pr = Pr^+-Pr^-$) int Pt/BLT/Pt/Si capacitors increased from $22 {\mu}C/cm^2$ to $30{\mu}C/ cm^2$ at 5V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. There was no drastic degradation in the polarization values after applying the retention read pulse for $10^{5.5}$ seconds. The capacitance-voltage data of $Pt/BLT/Y_2O_3/Si$ capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. The leakage current of the $Pt/BLT/Y_2O_3/Si$ capacitors annealed at $750^{\circ}C$ was about $510^{-8}A/cm^2$ at 5V. From the drain currents versus gate voltages ($V_G$) for $Pt/BLT/Y_2O_3/Si(100)$ FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile $V_G$ from 3V to 5V.

• 한국항해학회지
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• 제25권1호
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• pp.53-60
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• 2001

본 논문에서는 IMT-2000 수신주파수인 2.13~2.16 GHz 대역에서 초고주파용 수신장치로 사용되는 저잡음증폭기를 ㅈㄱ렬 피드백 기법과 저항결합회로를 이용하여 구현하였다. GaAs FET(Field Effect Transistor)의 소스단에 부가한 직렬 피드백은 저잡음증폭기의 저잡음특성과 입력반사계수가 작아졌으며, 또 저잡음증폭기의 안정도도 개선되었다. 저항결합회로는 반사되는 전력이 정합 회로내의 저항에서 소모되므로 입력단정합이 용이하였다. 저잡음증폭기의 저잡음증폭단은 GaAs FET인 ATF-10136, 고득증폭단은 내부정합된 MMIC인 VNA-25를 사용하였으며, 알루미늄 기구물 안에 유전율 3.5인테프론 기판에 초고주파회로와 자기바이어스 회로를 함께 장착시켰다. 이렇게 제작된 저잡음증폭기는 30 dB이상의 이득, 0.7dB 이하의 잡음지수, 17 dB의 Pldb, 1.5 이하의 입출력 정재파비를 얻었다.

• ETRI Journal
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• 제41권6호
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.269-269
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• 2010

$SnO_2$ 나노선은 n-type의 전기적 특성과 우수한 광 특성을 보이며, 전자소자, 광소자 뿐 아니라 다양한 종류의 가스 센서 등에 응용되고 있다. 그러나 $SnO_2$ 나노선은 공기중에서 전기적으로 불안정한 특성을 보이며, 도핑을 하지 않은 나노선 소자에서는 전자의 모빌러티가 높지 않다는 단점을 갖고 있다. 이를 개선하고자 본 연구에서는 화학기상증착법 (Chemical Vapor Deposition)으로 Sb을 도핑한 $SnO_2$ 나노선을 성장하여 전계방출효과 트랜지스터 (field effect transistor: FET)를 제작하여 전기적 특성과 UV 반응성의 변화를 측정하였다. Sb 도핑 양을 늘려감에 따라 전기적 특성이 반도체 특성에서 점점 금속 특성으로 변하는 것과 게이트 전압의 영향을 적게 받는 것을 확인하였다. 또한 도핑을 해준 $SnO_2$ 나노선의 경우 UV 반응과 회복 시간이 기존에 비하여 크게 감소하여 UV 센서에 더욱 적합해진 것을 확인하였다. 또한, 슬라이딩 트랜스퍼 공정을 이용하여 나노선을 원하는 기판에 정렬된 상태로 전이할 때 도핑한 나노선은 표면특성의 변화로 정렬도가 크게 감소하는 것을 확인하였고, 기판에 윤활제를 사용하여 정렬도를 높일 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.245-251
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• 2013

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.