• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.303-304
• /
• 2009

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine. ($F_{16}CuPc$) as an active layer. And we observed the surface morphology of the $F_{16}CuPc$ thin film. The $F_{16}CuPc$ thin film thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility.

• ETRI Journal
• /
• v.34 no.6
• /
• pp.950-953
• /
• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.1
• /
• pp.110-114
• /
• 2009

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different substrate temperature. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.303.1-303.1
• /
• 2014

좋은 전기적 특성을 가지면서 소자의 크기를 줄이기에 용이한 Gate-all-around (GAA) twin Si nanowire field-effect transistors (TSNWFETs)의 연구가 많이 진행되고 있다. Switching 특성과 단채널 효과가 없는 TSNWFETs의 특성은 GAA 구조의 본질적인 특성이다. TSNWFETs는 기존의 single Si nanowire TSNWFETs와 bulk FET에 비하여 Drive current가 nanowire의 지름에 많은 영향을 받지 않는다. 그러나 TSNWFETs의 전체 on-current는 훨씬 작고 nanowire의 지름이 작아지면서 줄어들게 되면서 소자의 sensing speed와 sensing margin 특성의 악화를 가지고 온다. GAA TSNWFETs의 제작 및 전기적 실험에 대한 연구는 많이 진행되었으나, GAA TSNWFETs의 전기적 특성에 대한 이론적 연구는 매우 적다. 본 연구에서는 GAA TSNWFETs의 nanowire 크기에 따른 전기적 특성을 관찰하였다. GAA TSNWFETs와 bulk FET의 전기적 특성을 양자역학을 고려하여 3차원 TCAD 시뮬레이션을 툴을 이용하여 계산하였다. GAA TSNWFETs와 bulk FET의 전류-전압 특성 계산을 통해 on-current 크기, subthreshold swing, drain-induced barrier lowering (DIBL), gate-induced drain leakage를 보았다. 전류가 흐르는 경로와 전기적 특성의 물리적 의미에 대한 연구를 위해 TSNWFETs에서의 전류 밀도, conduction band edge, potential 특성을 분석하였다. 시뮬레이션 결과를 통해 Switching 특성, 단채널 효과에 대한 면역 특성, nanowire의 단면적에 따른 전류 흐름을 보았다. nanowire의 크기가 작아지면서 DIBL이 증가하고 문턱전압과 전체 on-current는 감소하면서 소자의 특성이 악화된다. 이러한 결과는 GAA TSNWFETs의 전기적 특성을 이해하고 좋은 소자 특성을 위한 구조를 연구하는데 많은 도움이 될 것이다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.70-71
• /
• 2007

Analyzing pentacene field effect transistors (FETs) with Au source and drain electrodes as Maxwell-Wagner effect elements, electron and hole injection from the Au electrodes into the FET channel were examined using current-voltage (I-V), capacitance-voltage (C-V) and optical second harmonic generation (SHG) measurements. Based on these results, a mechanism of the hole and electron injection into pentacene from the Au electrodes and subsequently recombination mechanism with light-emitting in the pentacene layer are discussed, with taking into account the presence of trapped charges.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.3
• /
• pp.135-140
• /
• 2018

Atomically thin $MoS_2$ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, $MoS_2$ single-crystal as a transistor channel after transfer onto a $SiO_2/Si$ substrate. The $MoS_2$ FETs displayed n-channel characteristics with an electron mobility of $0.05cm^2/V-sec$, and a current on/off ratio of $I_{ON}/I_{OFF}{\simeq}5{\times}10^4$. Application of bottom-gate voltage stresses, however, increased the interface charges on $MoS_2/SiO_2$, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.217-220
• /
• 2001

CaN(gallium nitride) MODFET(modulation doped field effect transistor) large signal model was studied using Modified Materka-Kacprzak large signal MODFET model. using the Dambrine's method［3, at 45MHz-40㎓, Measured S-parameter and DC characteristics. based on measuring results, small signal parameter extraction was conducted. by the cold FET［4］method, measured parasitic elements were de-embedding. Extracted small signal parameters were modeled using modified Materka model, a sort of fitting function reproduce measuring results. to confirm conducted large signal modeling, modeled GaN MODFET's DC, S-parameter and Power characteristics were compared to measured results, respectively. by results were represented comparatively agreement, this paper showed that modified Materka model was useful in the GaN MODFET large signal modeling.

• Current Applied Physics
• /
• v.18 no.12
• /
• pp.1546-1552
• /
• 2018

The polymer nanocomposite as a gate dielectric film was prepared via sol-gel method. The formation of crosslinked structure among nanofillers and polymer matrix was proved by Fourier transform infrared spectroscopy (FT-IR). Differential thermal analysis (DTA) results showed significant increase in the thermal stability of the nanocomposite with respect to that of pure polymer. The nanocomposite films deposited on the p- and n-type Si substrates formed very smooth surface with rms roughness of 0.045 and 0.058 nm respectively. Deconvoluted $Si_{2s}$ spectra revealed the domination of the Si-OH hydrogen bonds and Si-O-Si covalence bonds in the structure of the nanocomposite film deposited on the p- and n-type Si semiconductor layers respectively. The fabricated n-channel field-effect-transistor (FET) showed the low threshold voltage and leakage currents because of the stronger connection between the nanocomposite and n-type Si substrate. Whereas, dominated hydroxyl groups in the nanocomposite dielectric film deposited on the p-type Si substrate increased trap states in the interface, led to the drop of FET operation.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.1
• /
• pp.10-16
• /
• 2016

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.354-355
• /
• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.