• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.1111-1114
• /
• 2006

We have developed a 2 inch LTPS-TFT AMOLED display with a top emission structure on a $50-{\mu}m-thick$ metal foil. The Active matrix back planes were fabricated with the p-channel LTPS TFT with a conventional pixel circuit consisting of 2 transistors and 1 capacitance. The p-channel TFTs on the metal foil exhibited the field-effect mobility of $22cm^2/Vs$. Finally, a images from prototype monochrome AMOLED displays are successfully presented, with $64{\times}88$ pixels and 56-ppi resolution.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.1162-1165
• /
• 2006

In this paper, the characteristics of polycrystalline silicon thin-film transistors (poly- Si TFTs) fabricated on polymer substrates are investigated. The a-Si films was laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated nMOS TFT showed field-effect mobility of ${\sim}30\;cm^2/Vs$, on/off ratio of $10^5$ and threshold voltage of 5 V.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1313-1316
• /
• 2005

In the present paper, it was investigated that adhesion layer on gate insulator could affect the electrical characteristics for the organic thin film transistors (OTFTs). The polyimide (PI) as organic adhesion layer was fabricated by using the vapor deposition polymerization (VDP) processing . It was found that electrical characteristics improved comparing OTFTs using adhesion layer to another. We researched adhesion layer as a function of thickness. For inverted-staggered top contact structure, field effect mobility, threshold voltage, and on-off current ratio of OTFTs using adhesion layer of PI 15 nm thickness on the gate insulator with a thickness of 0.2 ${\mu}m$ were about 0.5 $cm^2/Vs$, -0.8 V, and $10^6$, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.367-367
• /
• 2010

Electrical characteristics of Large-grain silicon with Ni-induced crystallization which gate insulator is made of 80 nm $SiO_2$ and 20 nm SiNx was fabricated and measured with different channel widths, channel length fixed $10{\mu}m$. Focusing on the changes of channel widths from $4{\mu}m$ to $40{\mu}m$. Field-effect mobility decreased from 111.30 to $94.10\;cm^2/V_s$ when the channel widths increased. Still threshold voltage was almost similar with -1.06V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.9
• /
• pp.677-680
• /
• 2012

The dependency of annealing temperature on the electrical performances in amorphous silicon-zinc-tin-oxide thin film transistors (SZTO-TFT) has been investigated. The SZTO channel layers were prepared by using radio frequency (RF) magnetron sputtering method with different annealing treatment. The field effect mobility (${\mu}_{FE}$) increased and threshold voltage ($V_{th}$) shifted to negative direction with increasing annealing temperature. As a result, oxygen vacancies generated in SZTO channel layer with increasing annealing temperature resulted in negative shift in $V_{th}$ and increase in on-current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.30 no.7
• /
• pp.413-416
• /
• 2017

We investigated solution-processed indium-yttrium-oxide (IYO) TFTs using apoly (methyl methacrylate) (PMMA) passivation layer. The IYO semiconductor solution was prepared with 0.1 M indium nitrate hydrate and 0.1 M yttrium acetate dehydrate as precursor solutions. The solution-processed IYO TFTs showed good performance: field-effect mobility of $13.13cm^2/Vs$, a threshold voltage of 8.2 V, a subthreshold slope of 0.93 V/dec, and a current on-to-off ratio of $7.2{\times}10^6$. Moreover, the PMMA passivation layers used to protectthe IYO active layer of the TFTs, did so without deteriorating their performance under ambient conditions; their operational stability and electrical properties also improved by decreasing leakage current.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.1
• /
• pp.146-151
• /
• 1995

We have studied the fabrication self aligned atmospheric pressure(AP) CVD a-Si thin film transistor with source-drain ohmic contact by using ion shower doping method. The conductivity is 6*10$^{-2}$S/cm when the acceleration voltage, doping time and doping temperature are 6kV, 90s and 350.deg. C, respectively. We obtained the field effect mobility of 1.3cm$^{2}$/Vs and the threshold voltage of 7V.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.5
• /
• pp.117-124
• /
• 1996

The .mu.c-Si:H films have been deposited by PeCVD at the various conditions such as hydrogen dilution ratio, substrate temperature and RF power density. Then, we studied their electrical and optical properties. Top gate hydrogenated micro-crystalline silicon thin film transistors($\mu$c-Si:H TFTs) using $\mu$-Si:H and a-SiN:H films have been fabricated by FECVD. The electrical characteristics of the devices have been investigated by semiconductor parameter analyzer and compared with amorphous silicon thin film transistors (a-Si:H TFTs). In this study, on/off current ratio, threshold voltage and the field effect mobility of the $\mu$c-Si:H TFT were $3{\times}10^{4}$, 5.06V and 0.94cm$^{2}$Vs, respectively.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.145-148
• /
• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.4
• /
• pp.33-39
• /
• 1997

The crystallization temperature of an amorphous silicon (a-Si) can be lowered down to 400.deg. C by a new method : Double-metal induced lateral crystallization (DMILC). The a-Si film was laterally crystallized from Ni and Pd deposited area, and its lateral crystallization rate reaches up to 0.2.mu.m/hour at that temperature and depends on the overlap length of Ni and Pd films; the shorter the overlap length, the faster the rate. Poly-Silicon thin film transistors (poly-Si TFT's) fabricated by DMILC at 400.deg. C show a field effect mobility of 38.5cm$^{3}$/Vs, a minimum leakage current of 1pA/.mu.m, and a slope of 1.4V/dec. The overlap length does not affect the characteristics of the poly-Si TFT's, but determines the lateral crystallization rate.