• Korean Journal of Applied Biomechanics
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• v.15 no.3
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• pp.31-49
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• 2005

The purpose of this study was to analyze the weight transfer patterns under the different golf swing types which are full swing control swing and putting stroke. Two women golfers participated in this study, one(165cm, 94.3kg)being classified as a low-handicap(LH)player, the other(165cm, 54.5kg) being classified as a high-handicap(HH) player. Both players are right-handed. Two force plates(Kistler, 9286AA) were synchronized with a motion capture system(Qualisys ProReflex MCU240). Anteriorposterior, mediolateral, and vertical forces were used as an indicator of the pattern of swing. Four discrete positions which are address, top of backswing impact, and finish were identified as an event and three phases which are backswing downswing, and follow-through between he events were also identified. The results showed that, at impact, the total force was 1.24BW ring the full swing 1.17BW during the control stroke, 1.00BW during the putting stroke. Depending on the golf swing types, the differences are existed. At impact, the distribution of forces is different with a low-handicap(LH) player and a high-handicap(HH) player. A LH player has 26% in right foot and 74% in left foot during the full swing 49% in right foot and 51% in left foot during the control swing 49% in right foot and 51% in left foot during the putting stroke. A HH, on the other hand, has 74% in right foot and 26% in left foot during the full swing 62% in right foot and 38% in left foot during the control swing 54% in right foot and 46% in left foot during the putting stroke. From address to top of backswing the amount of vertical forces are changed 43:57(right foot: left foot) to 76:24 during the full swing 47:53(right foot: left foot) to 75:25 during the control swing 50:50(right foot: left foot) to 54:46 during the putting stroke. The biggest weight transfer pattern took place in full swing and the control swing is next, and the putting stroke is the final.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.1-10
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• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.41-48
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• 2005

In this paper, we propose a new Low-Swing CVSL full adder for low power consumption. An $8\times8$ parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing the previous works, this circuit is reduced the power consumption rate of $13.1\%$ and the power-delay-product of $14.3\%$. The validity and effectiveness of the proposes circuits are verified through the HSPICE under Hynix $0.35{\mu}m$ standard CMOS process.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.2
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• pp.199-205
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• 2001

With the growth of BiCMOS technology in ASIC design, the issue of analyzing fault characteristics and testing techniques for BiCMOS circuits become more important In this paper, we analyze the fault models and characteristics of high speed full-swing BiCMOS circuits and the DFT technique to enhance the testability of full-swing high speed BiCMOS circuits is discussed. The SPICE simulation is used to analyze faults characteristics and to confirm the validity of DFT technique.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• Journal of International Academy of Physical Therapy Research
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• v.10 no.1
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• pp.1706-1710
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• 2019

Background: Despite frequent shoulder injuries of rotator cuff muscle of golfers by the result of overuse and poor swing mechanics, there is little research on shoulder specific rehabilitation exercises for injured rotator cuff muscle and golf swing Objective: To examined the effect of rehabilitation exercise for golfers on the X factor and ground reaction force (GRF) according to phase of the golf swing. Design: Crossover study Methods: The participants were 13 amateur golfers selected for a 4 week rehabilitation exercise for golfers. A rehabilitation exercise for golfers consisting of 5 steps and 4 items (sleeper stretch, full side plank, push up to plank, high plank knee unders) were applied to all participants. A three dimensional motion analyzer and force platform (SMART-E, BTS, Italy) were used to measure the X factor (angle between shoulder and pelvis at top of back swing) and GRF according to phase of the golf swing. All dependent variables were measured before and after exercise. The collected data was analyzed using the paired t test and SPSS 21.0. Results: The GRF had a statistically significant increase in the impact phase and ratio impact/weight after rehabilitation exercise for golfers (p<.05). The X-factor, GRF in top of back swing and finish were no significant differences between before and after exercise (p>.05). Conclusions: These results suggested that rehabilitation exercise for golfers was effective for increasing GRF in the impact phase and ratio impact/weight for amateur golfer.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Ergonomics Society of Korea
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• v.29 no.3
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• pp.337-345
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• 2010

The purpose of this study was to investigate the effects of sleep/wake behavior for shiftwork in air traffic controllers (ATCs) using wrist actigraph for ten workers on a continuous full-day three-team three-shift system of forward rotation including on-duty and off-duty periods. The wrist actigraph data were recorded for three days (one shift cycle) for each subject. The mean activity counts during an on-duty period progressively increased from the night, the swing, to the morning shifts. The doze length during on-duty periods showed decreases in the morning and swing shifts as compared to the night shift. Total sleep time (TST) and sleep efficiency (SE) during off-duty periods increased in the morning-1 and swing-night shift compared to the morning-2 shift. Finally, I discussed the role of doze-taking during the burden on night shift ATCs.