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Design of a Low-Power CVSL Full Adder Using Low-Swing Technique  

Kang Jang Hee (Department of Electronics Engineering Kangwon National University)
Kim Jeong Beom (Department of Electrical and Computer Engineering Kangwon National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.2, 2005 , pp. 41-48 More about this Journal
Abstract
In this paper, we propose a new Low-Swing CVSL full adder for low power consumption. An $8\times8$ parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing the previous works, this circuit is reduced the power consumption rate of $13.1\%$ and the power-delay-product of $14.3\%$. The validity and effectiveness of the proposes circuits are verified through the HSPICE under Hynix $0.35{\mu}m$ standard CMOS process.
Keywords
low power; low swing; full adder; CVSL; parallel multiplier;
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