• 한국정보통신학회논문지
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• 제13권9호
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• pp.1803-1810
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• 2009

본 논문은 OFDM을 사용하는 DVB-T 시스템에서 발생하는 IQ 불평형 오류를 추정하고 보상하는 문제를 Matlab으로 성능 평가하고, 이 중 IQ 불평형 오류 추정 보상 회로 부분을 Xilinx의 System Generator를 이용하여 FPGA로 설계 구현하여 성능을 비교 평가한 것이다. 모의실험 결과, Matlab 결과와 System Generator 결과 모두 IQ 불평형 오류가 우수하게 추정 보상됨을 확인하였으며, 또한 구현한 FPGA의 성능을 평가하기 위해 Hardware co-simulation 과정을 통해 Xilinx Sparta3 xc3s1000 fg676-4 target Device에 로딩하고, 타이밍 해석과 resource량도 확인함으로서 성능을 검증하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.758-761
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• 2004

This paper proposes a design and implementation of multiplierless digital PID (Proportional-Integral-Derivative) controller using FPGA (Field Programmable Gate Array) for controlling the speed of DC motor in digital system. The multiplierless PID structure is based on Distributed Arithmetic (DA). The DA is an efficient way to compute an inner product using partial products, each can be obtained by using look-up table. The PID controller is designed using MATLAB program to generate a set of coefficients associated with a desired controller characteristics. The controller coefficients are then included in VHDL (Very high speed integrated circuit Hardware Description Language) that implements the PID controller onto FPGA. MATLAB program is used to activate the PID controller, calculate and plot the time response of the control system. In addition, the hardware implementation uses VHDL and synthesis using FLEX10K Altera FPGA as target technology and use MAX+plusII program for overall development. Results in design are shown the speed performance and used area of FPGA. Finally, the experimental results can be shown when compared with the simulation results from MATLAB.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.548-550
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• 2006

This paper deals with the implementation of a small humanoid robot controller on the basis of Real Time Operating System(RTOS) and the FPGA. This controller was adapted to the humanoid robot with 25 DOFs, which are 12 DOFs in each leg, 8 DOFs in each arm, 3 DOFs in waist, and 2 DOFs in head. The robot actuators were used DX-117 servo motors that have all of the controller components in one module in order to simplify the control structure. In addition, the main controller is FPGA of Virtex4-FX from Xilinx, and ported on VxWorks that is kind of RTOS. It is essential to install this RTOS on the complex control system and to do control activity at the multitasking environments. This paper suggested the method of distributing the computational load in the humanoid robot controller using the FPGA and RTOS concepts. All of the control process was verified through the real action of the humanoid.

• 한국정보과학회논문지:시스템및이론
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• 제31권7호
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• pp.402-413
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• 2004

본 논문에서는 국내 표준 128비트 블록 암호화 알고리즘인 SEED를 소형 내장형(8-bit/ 16-bit) 시스템에 탑재하도록 저가의 FPGA로 구현하는 방법을 제안한다. 대부분 8-bit 또는 16-bit의 소규모 내장형 시스템들의 프로세서들은 그 저장용량과 처리속도의 한계 때문에 상대적으로 계산양이 많아 부담이 되는 암호화 과정은 별도의 하드웨어 처리기를 필요로 한다. SEED 회로가 다른 논리 블록들과 함께 하나의 칩에 집적되기 위해서는 적정한 성능을 유지하면서도 면적 요구량이 최소화되는 설계가 되어야 한다. 그러나, 표준안 사양의 구조대로 그대로 구현할 경우 저가의 FPGA에 수용하기에는 면적 요구량이 지나치게 커지게 되는 문제점이 있다. 따라서, 본 논문에서는 면적이 큰 연산 모듈의 공유를 최대화하고 최근 시판되는 FPGA 칩의 특성들을 설계에 반영하여 저가의 FPGA 하나로 SEED와 주변 회로들을 구현할 수 있도록 설계하였다. 본 논문의 설계는 Xilinx 사의 저가 칩인 Spartan-II 계열의 XC2S100 시리즈 칩을 대상으로 구현하였을 때, 65%의 면적을 차지하면서 66Mpbs 이상의 throughput을 내는 결과를 얻었다. 이러한 성능은 작은 면적을 사용하면서도 목표로 하는 소형 내장형 시스템에서 사용하기에 충분한 성능이다.

• 제어로봇시스템학회논문지
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• 제15권11호
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• pp.1137-1143
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• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2628-2630
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• 2002

This paper describes the design and implementation of the OFDM Modem using FPGA. The proposed OFDM method is based on IEEE 802.11a high-speed wireless LAN standard. The proposed and designed Pipeline FFT processor adopt the Radix-$2^2$SDF scheme. This method has a simple architecture and highly increases the calculation speed. And also it decreases the required number of registers. Therefore the proposed OFDM Modem reduces hardware size and improves the calculation speed. The OFDM Modem is implemented using $FLEX^{TM}$ FPGA.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.531-532
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• 2006

This paper presents the implementation of Real-time data acquisition system for dynamic characteristics of overhead contact wire in electric railway. The reconfigurable field-programmable gate array (FPGA) and LabVIEW graphical development tools have been used to Real-time monitoring system. The results from a field test show that the proposed technique and developed system can be practically applied to measure the assessment quantity or quantities on overhead contact lines for the online real-time process monitoring.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권3호
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• pp.191-193
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• 2005

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2013년도 춘계학술발표대회
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• pp.501-503
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• 2013

This project presents a concept of mobile robots using prototypes, computing proposal oriented to embedded systems implementation. We implement our system using GPS module, Ultrasonic sensor(range sensors), H-bridge dual stepper control, DTMF(Dual-tone Multi-Frequency ) and LCD module. In this paper we construct a mechanical simple mobile robot model, which can measure the distance from obstacle with the aid of sensor and should able to control the speed of motor accordingly. Modules were interfaced with FPGA(Field Programmable Gate Array) controller for hardware implementation.