FPGA Implementation of Recursive DFT based Phase Measurement Algorithm

DFT 연산 FPGA 모들에 기반한 위상 측정 앨고리즘의 구현

  • 안병선 (중앙대학교 전자전기공학부) ;
  • 김병일 (중앙대학교 전자전기공학부) ;
  • 장태규 (중앙대학교 전자전기공학부)
  • Published : 2005.03.01

Abstract

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

Keywords

References

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