• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.183-186
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• 2002

In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.85-95
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• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.5
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• pp.340-348
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• 1986

The design of two-dimensional zero-phase FIR digital filters by transformations is a popular and well-developed technique, but is suffers from the disadvantage that in its current form the filters with only four quadrant symmetry can not be designed exactly circular symmetry at frequencies far from the origin. it is shown how symmetry requirement for the filters with any number of dimensions can be fulfilled with arbbitrary percision by adapting transformation with the appropriate series expansions. this transformation has been known generally as the McClellan transformation. In this paper, a simple method for ensuring exelent circular symmetry at frequencies far from the origin is presented. This method which employs the Modified Mcclellan trnsformation for the design of 2-D FIR filter form 1-D FIR filters is quite useful for the design of 2-D FIR filters with multiple cutoff boundaries such as band-pass filters.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.93-98
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• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of Ubiquitous Convergence Technology
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• v.2 no.2
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• pp.59-66
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• 2008

In this study, Software Defined Radio (SDR) technology-based digital filterbank architecture applicable to a multiple-channel processing system such as a wireless mobile communication system using Code Division Multiple Access (CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response (FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter (BPF) to reconfigure another system. The feasibility of the algorithm is verified by computer simulation and by implementing a multiple-channel signal generator that is reconfigurable to other system profiles, including those of a Wideband Code Division Multiple Access (WCDMA) system and a CDMA system.

• Journal of Power Electronics
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• v.9 no.3
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• pp.430-437
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• 2009

This paper presents the dynamic characteristics of buck and buck-boost dc-dc converters with digital filters. At first, the PID, the minimum phase FIR filter and the IIR filter controls are discussed in the buck dc-dc converter. Comparisons of the dynamic characteristics between the buck and buck-boost converters are then discussed. As a result, it is clarified that the superior dynamic characteristics are realized in the IIR filter method. In the buck converter, the undershoot is less than 2% and the transient time is less than 0.4ms. On the other hand, in the buck-boost converter, the undershoot is about 3%. However, the transient time is approximately over 4ms because the output capacitance is too large to suppress the output voltage ripple in this type of converter.

• The Journal of the Convergence on Culture Technology
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• v.9 no.4
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• pp.563-568
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• 2023

ECG(electrocardiogram) is used to measure the rate and regularity of heartbeats, as well as the size and position of the chambers, the presence of any damage to the heart, and the cause of all heart diseases can be found. Because the ECG signal obtained using the ECG-KIT includes noise in the ECG signal, noise must be removed from the ECG signal to apply to the deep learning. In this paper, Noise included in the ECG signal was removed by using a lowpass filter of the Digital FIR Hamming window function. When the performance evaluation of the three activation functions, sigmoid(), ReLU(), and tanh() functions, which was confirmed that the activation function with the smallest error was the tanh() function, the elapsed time was longer when the batch size was small than large. Also, it was confirmed that result of the performance evaluation for the GRU model was superior to that of the LSTM model.