Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.06d
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- Pages.183-186
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- 2002
Implementation of efficient FIR filter using shift-and-add architecture and shared hardware
shift-and-add 구조와 연산 하드웨어 공유를 이용한 효율적인 FIR필터 구현
Abstract
In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.
Keywords