Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Area Efficient High Speed FIR Filter Design and Its Applications

면적 절약형 고속 FIR 필터의 설계 및 응용

  • Published : 2000.11.01
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Abstract

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

FIR 디지털 필터는 DSP에서 사용되는 중요한 회로 중에 하나이며, 보다 효율적인 연산을 위한 여러 가지 구조가 제안되었다. 본 논문에서는 필터 연산을 고속으로 수행하면서도 면적을 줄일 수 있는 필터 구조를 제안한다. Transposed 구조를 적용하여, 고속의 연산이 가능토록 하는 기본 구조를 사용하였다. 여기에, 이중 경로 레지스터 라인이라는 두 개의 연산 패스가 존재하여 다양한 종류의 필터 연산이 가능하며, 이 필터를 연속적으로 이어 사용할 수 있는 cascade 구조도 지원한다. Truncated Booth 곱셈기라는 면적 절약형 곱셈기를 사용하여 회로 크기를 줄일 수 있었다. 이중 경로 레지스터 라인과 truncated 곱셈기를 사용하여 주어진 조건에 최적화된 필터를 설계할 경우에 회로의 크기가 더 줄어 들수 있음을 확인하였다.

Keywords

References

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