• 제목/요약/키워드: FETs

검색결과 222건 처리시간 0.034초

AFM을 이용한 나노 패턴 형성과 크기에 따른 광특성 시뮬레이션 (Simulations of Optical Characteristics according to the Silicon Oxide Pattern Distance Variation using an Atomic Force Microscopy (AFM))

  • 황민영;문경숙;구상모
    • 한국전기전자재료학회논문지
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    • 제23권6호
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    • pp.440-443
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    • 2010
  • We report a top-down approach based on atomic force microscopy (AFM) local anodic oxidation for the fabrication of the nano-pattern field effect transistors (FETs). AFM anodic oxidation is relatively a simple process in atmosphere at room temperature but it still can result in patterns with a high spatial resolution, and compatibility with conventional silicon CMOS process. In this work, we study nano-pattern FETs for various cross-bar distance value D, from ${\sim}0.5\;{\mu}m$ to $1\;{\mu}m$. We compare the optical characteristics of the patterned FETs and of the reference FETs based on both 2-dimensional simulation and experimental results for the wavelength from 100 nm to 900 nm. The simulated the drain current of the nano-patterned FETs shows significantly higher value incident the reference FETs from ${\sim}1.7\;{\times}\;10^{-6}A$ to ${\sim}2.3\;{\times}\;10^{-6}A$ in the infrared range. The fabricated surface texturing of photo-transistors may be applied for high-efficiency photovoltaic devices.

Polymeric Flexible Field Effect Transistors using Oriented Poly(3-hexylthiophene-2,5-diyl)

  • Lee, Yeong-Beom;Shim, Hong-Ku
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.637-640
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    • 2008
  • The properties of oriented poly(3-hexylthiophene-2,5-diyl) in field effect transistors (FETs) have been investigated through mechanical stretching process as the original. Silicon-based FETs shown high mobility of $0.02\;cm^2/V$ s after thermal treatment and $0.0092\;cm^2/V$ s at r.t. PET-based FETs were expected to show a similar performance in mobility to that of silicon-based FETs.

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Self Heating Effects in Sub-nm Scale FinFETs

  • Agrawal, Khushabu;Patil, Vilas;Yoon, Geonju;Park, Jinsu;Kim, Jaemin;Pae, Sangwoo;Kim, Jinseok;Cho, Eun-Chel;Junsin, Yi
    • 한국전기전자재료학회논문지
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    • 제33권2호
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    • pp.88-92
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    • 2020
  • Thermal effects in bulk and SOI FinFETs are briefly reviewed herein. Different techniques to measure these thermal effects are studied in detail. Self-heating effects show a strong dependency on geometrical parameters of the device, thereby affecting the reliability and performance of FinFETs. Mobility degradation leads to 7% higher current in bulk FinFETs than in SOI FinFETs. The lower thermal conductivity of SiO2 and higher current densities due to a reduction in device dimensions are the potential reasons behind this degradation. A comparison of both bulk and SOI FinFETs shows that the thermal effects are more dominant in bulk FinFETs as they dissipate more heat because of their lower lattice temperature. However, these thermal effects can be minimized by integrating 2D materials along with high thermal conductive dielectrics into the FinFET device structure.

벌크 FinFET의 기술 동향 및 이슈 (Trend and issues of the bulk FinFET)

  • 이종호;최규봉
    • 진공이야기
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    • 제3권1호
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    • pp.16-21
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    • 2016
  • FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

쇼트키 장벽 트랜지스터의 빛 조사에 따른 전기적 특성 연구 (Electric characteristics of Schottky barrier Field Effect Transistors with Halogen and Deuterium lamp)

  • 황민영;구상모
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.348-348
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    • 2010
  • Nanostructures have great potential in various devices due to the their promising electronic and optical properties. Nano-patterned the front surface of a solar cell generally results in improved performance, mostly due to an increase in the short-circuit current by the incident photons strike the cell surface at an angle. In this work, we investigate AFM-assisted nano-patterned field effect transistors (FETs) with vairous silicon oxide distance value D, from ${\sim}0.5{\mu}m$ to $1{\mu}m$. Also, we compared the electro-optical characteristics of the patterned FETs and the non-patterned FETs (reference device) based on both 2-dimensional simulation and experimental results for the wavelength from 100nm to 900nm. In addition, we report electric characteristics for illuminated surface in schottky barrier field effect transistors (SB-FETs).

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Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

  • An, TaeYoon;Choe, KyeongKeun;Kwon, Kee-Won;Kim, SoYoung
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권5호
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    • pp.525-536
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    • 2014
  • Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

Giant Piezoelectric Nanocomposites Integrated in Physically Responsive Field-effect Transistors for Pressure Sensing Applications

  • Tien, Nguyen Thanh;Trung, Tran Quang;Kim, Do-Il;Lee, Nae-Eung
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.550-551
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    • 2012
  • Physically responsive field-effect transistors (physi-FETs), which are sensitive to physical stimuli, have been studied for decades. However, the primary issue of separating responses by sensing materials from interferences by other subcomponents in a FET transducer under global physical stimuli has not been completely resolved. Recent challenges of structural design and employing smart materials with a large electro-physical coupling effect for flexible physi-FETs still remain. In this article, we propose directly integrating nanocomposites of barium titanate (BT) nanoparticles (NPs) and highly crystalline poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) as gate dielectrics into flexible organic FETs to precisely separate and quantify tiny variations of remnant polarization caused by mechanical stimuli. Investigations under static stimuli resulted in first-reported giant-positive piezoelectric coefficients of d33 up to 960 pC/N, presumably due to significant contribution of the intrinsic piezoelectricity of BT NPs and P(VDF-TrFE) crystallites. This approach provides a general research direction, and not limited to physic-FETs.

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Precise pressure sensor using piezoelectric nanocomposites integrated directly in organic field-effect transistors

  • Tien, Nguyen Thanh;Trung, Tran Quang;Seol, Young-Gug;Lee, Nae-Eung
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.500-500
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    • 2011
  • With recent advances in flexible and stretchable electronics, the development of physically responsive field-effect transistors (physi-FETs) that are easily integrated with transformable substrates may enable the omnipresence of physical sensing devices in electronic gadgets. However, physical stimuli typically induce whole sensing physi-FET devices under global influences that also cause changes in the parameters of FET transducers, such as channel mobility and dielectric capacitance that prevent proper interpretations of response in sensing materials. Extended-gate structures with isolated stimuli have been used recently in physi-FETs to demonstrate performances of sensing materials only. However, such approaches are limited to prototype researches since isolated stimuli rarely occur in real-life applications. In this report, we theoretically and experimentally demonstrated that integrating piezoelectric nanocomposites directly into flexible organic FETs (OFETs) as gate dielectrics provides a general research direction to physi-FETs with a simple device structure and the capability of precisely investigating functional materials. Measurements with static stimulations, which cannot be performed in conventional systems, exhibited giant-positive d33 values of nanocomposites of barium titanate (BT) NPs and poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)).

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Design Consideration of Body-Tied FinFETs (${\Omega}$ MOSFETs) Implemented on Bulk Si Wafers

  • Han, Kyoung-Rok;Choi, Byung-Gil;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권1호
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    • pp.12-17
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    • 2004
  • The body-tied FinFETs (bulk FinFETs) implemented on bulk Si substrate were characterized through 3-dimensional device simulation. By controlling the doping profile along the vertical fin body, the bulk FinFETs can be scaled down to sub-30 nm. Device characteristics with the body shape were also shown. At a contact resistivity of $1{\times}10^{-7}\;{\Omega}\;cm^2$, the device with side metal contact of fin source/drain showed higher drain current by about two. The C-V results were also shown for the first time.

스프레이 공정을 이용한 nc-ZnO/ZnO 전계효과트랜지스터의 광학적 노출에 대한 열화 현상 분석 (The Instability Behaviors of Spray-pyrolysis Processed nc-ZnO/ZnO Field-effect Transistors Under Illumination)

  • 조준희
    • 반도체디스플레이기술학회지
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    • 제22권1호
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    • pp.78-82
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    • 2023
  • Metal oxide semiconductor (MOS) adapting spray-pyrolysis deposition technique has drawn large attention based on their high quality of intrinsic and electrical properties in addition to simple and low-cost processibility. To fully utilize the merits of MOS field-effect transistors (FETs) , transparency, it is important to understand the instability behaviors of FETs under illumination. Here, we studied the photo-induced properties of nc-ZnO/ZnO field-effect transistors (FETs) based on spray-pyrolysis under illumination which incorporating ZnO nanocrystalline nanoparticles into typical ZnO precursor. Our experiments reveal that nc-ZnO in active layer suppressed the light instabilities of FETs.

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