1 |
T. Park, D. G. Park, J. H. Chung, H. J. Cho, E. J. Yoon, S. M. Kim, J. D. Choi, J. H. Choi, B. M. Yoon, J. J. Han, B. H. Kim, S. Choi, K. N. Kim, E. Yoon, and J. H. Lee, 'PMOS Body-Tied FinFET (Omega MOSFET) Characteristics.' in Tech. Dig. of DRC, II.B-2, 2003.
|
2 |
T. Park, H.J. Cho, J.D. Chae, S.Y. Han, S.M. Jung, J.H. Jeong, B.Y. Nam, O.I. Kwon, J.N. Han, H.S. Kang, M.C. Chae, G.S. Yeo, S.W. Lee, D.Y. Lee, D. Park, K. Kim, E. Yoon, and J.H. Lee, 'Static Noise Margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs),' in Tech. Dig. of IEDM, pp.27-30, 2003.
DOI
|
3 |
Jong-Ho Lee, Tai-su Park, Euijoon Yoon and Young June Park, 'Simulation Study of a New body-tied FinFET(Omega MOSFET) using bulk Si wafer', in Proc. of Silicon Nanoelectronics Workshop, pp.102-103, 2003.
|
4 |
SILVACO International, ATLAS User' s Manual-Device Simulation Software (Santa Clara, 2000)
|
5 |
Jong-Tae Park, J.-P. Colinge, C.H. Diaz, 'Pi-Gate SOI MOSFET,' IEEE Electron Device Letters, vol. 22, pp. 405-406, Aug. 2001.
DOI
ScienceOn
|
6 |
Fu-Liang Yang, Hao-Yu Chen, Chenming Hu, '25 nm CMOS Omega FETs' in Tech. Dig. of IEDM, pp. 255-258, 2002.
DOI
|
7 |
J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, 'Silicon-on-insulator 'gate-all-around device',' in Tech. Dig. of IEDM , pp. 595-598, 1990.
DOI
|
8 |
Tai-su Park, Euijoon Yoon, and Jong-Ho Lee, 'A 40 nm body-tied FinFET (Omega MOSFET) using bulk Siwafer,' Physica E19, pp.6-12, July 2003
DOI
ScienceOn
|
9 |
Tai-su Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S.H. Hong,S. J. Hyun, Y. G. Shin, J. N. Han, U I. Chung, J. T. Moon, E. Yoon, and Jong-Ho Lee, 'Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers' in Tech. Dig. of Sympo. on VLSI Tech., T10A3, 2003.
|
10 |
Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu, 'Nanoscale CMOS spacer FinFET for the terabit era,' IEEE Electron Device Letters, vol. 23, pp. 25-27, Jan. 2002
DOI
ScienceOn
|
11 |
B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios and R. Chau, 'Tri-gate fully-depleted CMOS transistors: fabrication, design and layout,' in Tech. Dig. of Sympo. on VLSI Tech., pp. 133-134, 2003.
|