• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.508-517
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• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

• 전자공학회논문지
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• 제51권7호
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• pp.71-81
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• 2014

본 논문에서는 삼차원 소자 시뮬레이터(Sentaurus)를 이용하여 tri-gate FinFET의 fin과 소스/드레인 구조의 변화에 따른 소자의 성능을 분석하였다. Fin의 구조가 사각형 구조에서 삼각형 구조로 변함에 따라, fin 단면의 전위 분포의 차이로 문턱 전압이 늘어나고, off-current가 72.23% 감소하고 gate 커패시턴스는 16.01% 감소하였다. 소스/드레인 epitaxy(epi) 구조 변화에 따른 성능을 분석하기 위해, epi를 fin 위에 성장시킨 경우(grown-on-fin)와 fin을 etch 시키고 성장시킨 경우(etched-fin)의 소자 성능을 비교했다. Fin과 소스/드레인 구조의 변화가 회로에 미치는 영향을 살펴보기 위해 Sentaurus의 mixed-mode 시뮬레이션 기능을 사용하여 3단 ring oscillator를 구현하여 시뮬레이션 하였고, energy-delay product를 계산하여 비교하였다. 삼각형 fin에 etched 소스/드레인 epi 구조의 소자가 가장 작은 ring oscillator delay와 energy-delay product을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.292-293
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• 2013

Sub 10-nm thick of Si plate is simulated with the software for Nanowire Field Effect Transistor (FET) device simulation. With usual single crystal Si technology, it is difficult to realize flexible electronic devices. Here, we suggest a FET device based on thinned Si layer. The simulation implied a practical limitation of the Si plate thickness for flexible devices as 2 nm. With around this thickness, Si plate may have much flexibility than existing bulk MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• Journal of Magnetics
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• 제7권1호
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• pp.4-8
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• 2002

The magnetoresistance (MR) and the magnetization reversal of a lateral spin-injection device based on a spin-polarized field effect transistor (spin FET) have been investigated. The device consists of a two-dimensional electron gas (2DEG) system in an InAs single quantum well (SQW) and two ferromagnetic $(Ni_{80}Fe_{20})$ contacts: all injector (source) and a detector (drain). Spin-polarized electrons are injected from the first contact and, after propagating through the InAs SQW are collected by the second contact. By engineering the shape of the permalloy contacts, we were able to observe distinct switching fields $(H_c)$ from the injector and the collector by using scanning Kerr microscopy and MR measurements. Magneto-optic Kerr effect (MOKE) hysteresis loops demonstrate that there is a range of magnetic field (20~60 Oe), at room temperature, over which the magnetization in one contact is aligned antiparallel to that in the other. The MOKE results are consistent with the variation of the magnetoresistance in the spin-injection device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.6-7
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• 2008

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450V power MOSFET devices by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5\times10^{14}cm^{-3}$, size of $600{\mu}m^2$ with 4.5 $\Omega$, and off-state leakage current below 50 ${\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods is meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.751-753
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• 2007

최근에 유기물 전계효과 트랜지스터의 연구는 전자 소자 분야에서 널리 알려져 있다. 특히 본 연구에서는 CuPc 물질을 활성층으로 사용하여 Organic FET 소자를 제작하였다. Source와 Drain 전극을 Au와 Al을 사용하여 FET 소자의 전기적 특성을 비교하였다. CuPc FET 소자에서 CuPc 활성층의 두께는 40nm로 고정하였고, Au와 Al 전극의 두께는 200nm로 하여 소자를 제작하였다. 또한 C-V 특성을 측정하여 CuPc 유기물 층과 $SiO_2$ 절연층 계면에서의 특성 변화를 관측하였다. Au를 전극으로 사용한 FET 소자에서는 전형적인 FET 특성 곡선을 관측할 수 있었으나, Al을 전극을 사용한 FET 소자에서는 누설 전류가 흐르고 있음을 확인 할 수 있었다.

• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.57-61
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• 2009

This paper has presented the subthreshold current model of FinFET using the potential variation in the doped channel based on the analytical solution of three dimensional Poisson's equation. The model has been verified by the comparison with the data from 3D numerical device simulator. The variation of subthreshold current with front and back gate bias has been studied. The variation of subthreshold swing and threshold voltage with front and back gate bias has been investigated.