• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.3
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• pp.286-291
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• 2015

LLC resonant converter is used to control laser output power in Nd:YAG laser. Zero voltage switching (ZVS) is implemented to minimize the switching loss which is adopting the LLC resonant converter. In the spot welding processing of metal thin films, the processing quality is decided by the laser beam output energy of single pulse. We decide to the 50 [J] as the single pulse laser beam energy. Laser output power is investigated and experimented by changing the output current. That current is controled by the charging voltage of capacitor. From those results, we obtained the maximum laser output of 58.2 [J] and the conversion efficiency of 2.52% at the discharge voltage of 620V and the discharge current of 861 [A] and the pulse repetition rate of 1 [Hz] at the charging capacitor of 12,000 [${\mu}F$].

• Journal of Power Electronics
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• v.12 no.1
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• pp.88-97
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• 2012

This paper presents a method for the digital control of a high power factor AC/DC converter employing the power balance control technique to achieve a fast response of the output voltage control. To avoid the effects of an output voltage ripple in the voltage control loop, the average output voltage is sampled and used as a feedback signal for the output voltage controller. The proposed control technique was verified by simulations using MATLAB/Simulink and its implementation was realized by a dsPIC30F4011 digital signal processor to control a CUK topology AC/DC converter with a 48V output voltage and a 250 W output power. The experimental results agree with the simulation results. The proposed control technique achieves a fast transient response with a lower line current distortion than is achieved when using a conventional proportional-integral controller and the power balance control technique with the conventional sampling method.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.194-199
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• 1997

When voltage or current gets out of the magnetic sensor as it is, we have often faced the problems such as introduction of noise and loss of voltage. In order to reduce these problems, a 2 drain MAGFET operating in the saturation region and fabricated by CMOS process, the system of I/V converter, VCO with operational amplifier, and V/F conversion circuits with Schmitt Trigger are designed and fabricated in one package. The absolute sensitivity of magnetic sensor shows 1.9 V/T and the product sensitivity is $3.2{\times}10^{4}\;V/A{\cdot}T$. The characteristic of V/F conversion is very stabilized and has the value of 190 kHz/T.

• Journal of Power Electronics
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• v.11 no.4
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• pp.533-541
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• 2011

The redundant operation of a parallel AC to DC converter via a serial communication bus is presented. The proposed system consists of three isolated CUK power factor correction modules. The controller for each converter is a dsPIC30F6010 microcontroller while a RS485 communication bus and the clock signal are used for synchronizing the data communication. The control strategy of the redundant operation relies on the communication of information among each of the modules, which communicate via a RS485 serial bus. This information is received from the communication checks of the converter module connected to the system to share the load current. Performance evaluations were conducted through experimentation on a three-module parallel-connected prototype, with a 578W load and a -48V dc output voltage. The proposed system has achieved the following: the current sharing is quite good, both the transient response and the steady state. The converter modules can perform the current sharing immediately, when a fault is found in another converter module. In addition, the transient response occurs in the system, and the output voltages are at their minimum overshoot and undershoot. Finally, the proposed system has a relatively simple implementation for the redundant operation.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.4
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• pp.322-331
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• 2002

In this paper, a single-phase to three-phase PWM converter topology using a single-phase half-bridge PWM rectifier and a 2-leg inverter for low cost three-phase induction motor drives is proposed. In addition, the source voltage sensor is eliminated with a state observer which controls the deviation between the model current and the system current to be zero. The converter topology is of lower cost than the conventional one, which gives sinusoidal input current, unity power factor, dc output voltage control, bidirectional power flow and VVVF output voltage. The experimental results for V/F control of 3Hp induction motor drives have been shown.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1719-1721
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• 2005

현재 지구 환경 오염에 관한 관심이 증가하면서, 공해가 없는 자연 에너지원에 대한 연구가 많이 진행되고 있다. 그 중에서도 태양전지 분야중 염료감응형 태양전지(DSC)는 Si계 태양전지와 비교하여 낮은 제조비용등 여러 가지 이유로 최근 많은 연구가 진행되고 있다. 따라서 DSC 발전 시스템의 효율 향상이 요구된다. 본 연구에서는 태양전지 분야 중에서 독립적인 발전설비가 필요한 도서 및 산간 지역에 전력을 안정적으로 공급할 수 있는 소형발전용의 설비로 "전압 및 전류의 피드백을 통한 DSC Cell의 독립전원의 안정화"에 관해 연구하였다. DSC Cell측의 DC입력을 받아 Boost Converter로 승압 후 Full Bridge 인버터를 사용하여 단상 220V 60Hz의 상용전원으로 변환하였다. 여기서는 32Bit 마이크로프로세서인 DSP TMS320F2812의 A/D변환기능을 이용하여 Boost Converter의 스위칭과 Full Bridge 인버터의 스위칭을 제어하였다. 특히 TMS320F2812의 RTC(Real Time Clock)를 이용하여 출력전압의 안정성 향상에 주목적을 두었다. 실험결과 출력단에서는 220V 변동범위 0.2% 주파수 60Hz의 상용전원을 얻었으며, 프로그램의 개선을 통하여 출력전압의 변동범위를 감소시켜야 될 것이다.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.