• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.45-46
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• 1995

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.420-423
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• 1987

Planarization in multilevel metallization is very important to smooth out topographic undulations by conductors, dielectrics, contacts, and vias. One of methods for planarizing interdielectrics, such as the etchback process of the double layer composed of the photoresist on the interdielectric low temperature oxide was introduced. The step heights of interdielectrics before and after etch-back process was measured by Scanning Electron Microscope, and the degree of planarization was analyzed, comparing the differences of the step heights. In this experiment, the degree of planarization was controlled up to about 0.9.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.1-4
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• 2007

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.

• 한국재료학회지
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• 제2권3호
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• pp.228-238
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• 1992

서브마이크론 설계규칙을 갖는 소자의 이층 배선 공정에서 다챔버 장비를 이용한 금속 층간절연막의 공극없는 평탄화를 위하여 PECVD와 $O_3$ ThCVD산화막의 증착시 층덮힘성을 연구하였다. 산화막의 두께가 증가됨에 따라 변화되는 순간단차비의 개념을 도입하여 공극형성의 개시점을 예측할 수 있는 관계식을 모델링하였고, 금속배선간격의 초기 단차비가 다양한 패턴에서 산화막의 두께에 따른 순간 단차비의 변화를 조사하였다. 모델링 검정결과 $5^{\circ}$이하의 re-entrant각을 갖는 TEOS에 의한 PECVO 산화막의 순간단차비가 모델링에 잘 일치하였다. 공극없는 평탄화는 제1층의 PECVD 산화막의 순간 단차비를 0.8이하로 유지하거나 Ar sputter식각을 통하여 산화막의 모서리에 경사를 준후 층덮힘성이 우수한 $O_3$ ThCVD산화막을 증착함으로써 가능하였다. $O_3$ ThCVD산화막의 etchback이 non etchback공정에 비하여 via접쪽저항체인에서 높은 수율을 보였으며, via접촉저항은 $0.1~0.3{\Omega}/{\mu}m^2$로 나타났다.

• 한국진공학회지
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• 제4권S1호
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• pp.151-156
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• 1995

0.5$\mu$m 이하 급의 device에서 TEOS/O3 BPSG 박막을 층간절연막(Interlayer Dielectric)으로 사용하여, 평탄화를 위해 etchback 공정을 적용할 때 BPSG 박막이 가지는 구조적, 화학적 불안정성으로 인해 B,P 농도의 변화나 crack 발생 현상이 일어날 수 있다. 본 실험에서는 이러한 현상을 억제하기 위해 농도를 달리한 이층막의 증착, PR strip 시에 사용하는 wet chemical의 변경 및 증착후 치밀화(densificaiton)공정추가 등의 방법을 사용하였으며, 이에 따른 박막 특성의 변화를 조사하였다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (2)
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• pp.674-676
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• 1998

소자가 sub-quarter um급으로 축소됨에 따라 STI(Shallow Trench Isolation) 기술은 고 집적도의 ULSI 구현에 있어서 중요한 격리 방법으로 많이 사용되고 있다. 현재의 STI 기술은 주로 실리콘 기판을 식각 후 절연물질로 빈 공백이 없이 채우는 (void-free gap filling) 방법 [1,2]과 절연물질을 다시 표면 근처까지 CMP(Chemical Mechnical Polishing)로 etchback하여 평탄화를 하는 방법이 주요한 기술이 되고 있다. 또한 STI 구조로된 격리구조에서 만들어진 MOSFET의 전기적인 특성은 트랜치 격리의 상부 부분의 형태와 gap-filling 물질에 따라 큰 영향을 받게된다. 따라서 본 논문에서는 STI 구조로 만들어진 격리 구조에서 MOSFET의 hump 특성에 관해 연구하였다. 그 결과 hump는 STI 모서리에서 필드 옥사이드의 recess에 의한 모서리 부분에서의 전계 집중과 boron의 segration에 기인한 농도 감소로 인해 hump가 발생하는 것으로 나타났다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.167-171
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• 1996

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily achieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etchback process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurement of planarity. Moreover, it will contribute to analyze planarization characteristics and establish CMP model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• 센서학회지
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• 제14권3호
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• pp.206-210
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• 2005

The SOI structure with buried alumina was fabricated by ALD followed by bonding and etchback process. The interface of alumina and silicon was analyzed by CV measurements and cross section was investigated by SEM analysis. The density of interface state of alumina and silicon was 2.5E11/$cm^{2}$-eV after high temperature annealing for wafer bonding. It was confirmed that the surface silicon layer was completely isolated from substrate by cross section SEM and AES depth profile. The device on this alumina SOI structure would have better thermal properties than that on conventional SOI due to higher thermal conductivity of alumina than that of silicon dioxide.