• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.622-625
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• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.10-10
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• 2010

ESD (Electrostatic Discharge) phenomenon occurs in everywhere and especially it damages to semiconductor devices. For ESD protection, there are some devices such as diode, GGNMOS (Gate-Grounded NMOS), SCR (Silicon-Controlled Rectifier), etc. Among them, diode and GGNMOS are usually chosen because of their small size, even though SCR has greater current capability than GGNMOS. In this paper, a novel SCR is proposed on the SOI (Silicon-On-Insulator) structure which has $1{\mu}m$ film thickness. In order to design and confirm the proposed SCR, TSUPREM4 and MEDICI simulators are used, respectively. According to the simulation result, although the proposed SCR has more compact size, it's electrical performance is better than electrical characteristics of conventional GGNMOS.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.391-392
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• 2008

A SPICE-based 3-dimensional circuit model of Light-Emitting Diode(LED) was modified include the reverse breakdown properties. The new model is found to be accurate to study the failure mechanisms of LEDs under electrostatic discharge (ESD) and electronic overstress (EOS). It was found that the permanent damages under heavy reverse stress is mainly due to the high electric field strength in P-GaN layer.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.37-47
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• 1997

Utilizing 2-dimensional device simulations incorporating lattic eheating models, we analyzed in detail the DC breakdown characterisics of NMOS trasistors with different structures, which are commonly used as ESD protection transistors. The mechanism leading to device failure resulting from electrostatic discharge was explained by analyzing the 1st and 2nd breakdown characteristics of LDD devices. Also a criteria for more robust designs of NMOS transistor structures against ESD was suggested by examining the characteristics changes with changes in structural parameters such as the LDD doping concentration, the drain junction depth, the distance between source/drain contacts, and the source junction area.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.1
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• pp.34-38
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• 1999

In order to develop a thin type ESP(Electrostatic Precipitator) for high efficient air-conditioner with low concentration of ozone generation, collecting electrode spacing should be narrower than that from Deutsch formula and minimizes discharge current in ionizer. In this paper, the effect of applied voltage on the precipitation efficiency and ozone concentration of scroll type ESP was studied. As a result, precipitation efficiency(one pass) was improved by about 30[%] from increment of collector voltage(3.5[㎸]). Precipitation efficiency was increased with increasing ionizer voltage. And after some point, the efficiency was saturated. At the point, voltage and ionizer current was 5.2[㎸] and 95$[\muA]$ per meter respectively. At these applied voltage conditions, ozone concentration was saturated about 0.01[ppm] after 3 hours in 23$[m^3]$ closed room test.

• ETRI Journal
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• v.31 no.6
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• pp.725-731
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• 2009

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.587-588
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• 2006

This paper presents the new structural zener triggered silicon-controlled rectifier (ZTSCR) electrostatic discharge (ESD) protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. The proposed ZTSCR has the triggering voltage of 4V. In the ESD event, this proposed novel ZTSCR ESD protection device could trigger quickly and provide an effective discharging path.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.227-231
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• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.288-292
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• 2002

We propose the new type of on-chip ESD protection method for RF applications. By using the properties of RF circuits, we can use the short-circuited stub as ESD protection device in front of the DC blocking capacitor Specially, we can use short-circuited stub as the portion of the matching circuit so to reduce the and various parameters of the transmission line. This new type ESD protection method is very different from the conventional ESD protection method. With the new type ESD protection method, we remove the parasitic capacitance of ESD protection device which degrade the performance of core circuit.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.8
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• pp.587-595
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• 1998

Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.