• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2033-2044
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• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

• The Magazine of the IEIE
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• v.36 no.9
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• pp.61-69
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• 2009

본 기고에서는 반도체 3D IC에서 저전력, 고속 신호 전송을 가능하게 하는 다양한 인터페이스 기술에 대하여 알아보았다. Micro-bump나 TSV와 같이 유선으로 신호를 전송하는 방법과, capacitance나 inductance coupling을 이용하여 무선으로 전송하는 기술을 살펴보았다. 최근 TSV 공정 기술이 많이 발전하여, 앞으로 TSV 인터페이스에 기반한 3D IC가 많이 나올 것으로 기대된다. 무선 인터페이스를 사용할 경우, 특히 inductance coupling을 이용한 경우, 낮은 vdd로도 신호전송이 가능하고, pulse width를 줄일 수 있으며, ESD 보호회로가 필요없어, 저전력으로 신호를 전송할 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1858-1864
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• 2009

In this paper, we design a non-volatile memory IP, 1-kb one-time programmable (OTP) memory, used for power management ICs. Since a conventional OTP cell uses an isolated NMOS transistor as an antifuse, there is an advantage of it big cell size with the BCD process. We use, therefore, a PMOS transistor as an antifuse in lieu of the isolated NMOS transistor and minimize the cell size by optimizing the size of a OTP cell transistor. And we add an ESD protection circuit to the OTP core circuit to prevent an arbitrary cell from being programmed by a high voltage between the terminals of the PMOS antifuse when the ESD test is done. Furthermore, we propose a method of turning on a PMOS pull-up transistor of high impedance to eliminate a gate coupling noise in reading a non-programmed cell. The layout size of the designed 1-kb PMOS-type antifuse OTP IP with Dongbu's $0.18{\mu}m$ BCD is $129.93{\times}452.26{\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1297-1303
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling, ESD of each sensor pixel. The 128${\times}$l44 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Proceedings of the IEEK Conference
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• summer
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• pp.82-85
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• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.249-252
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog to comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an exective isolation strategy for removing noise and signal coupling of each sensor pixel. The 128$\times$144 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.109-114
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• 2004

This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.366-372
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• 2017

In this paper, the analysis of baluns that are inevitably required to design a differential low noise amplifier, The balun converts a single signal input from the antenna into a differential signal, which serves as an input to the differential amplifier. In addition, it protects the circuit from ESD(Electrostatic Discharge) coming through the antenna and helps with input matching. However, in the case of a passive balun used in general, since the AC signal is transmitted through electromagnetic coupling formed between two metal lines, it not only has loss without gain but also has the greatest influence on the total noise figure of the receiving end. Therefore, the design of a balun in a low-noise amplifier is very important, and it is important to design a balun in consideration of line width, line spacing, winding, radius, and layout symmetry that are necessary. In this paper, the factors to be considered for improving the quality factor of balun are summarized, and the tendency of variation of resistance, inductance, and capacitance of the balun according to design element change is analyzed. Based on the analysis results, it is proved that the design of input balun allows the design of low noise, high gain differential amplifier with gain of 24 dB and noise figure of 2.51 dB.