• Journal of IKEEE
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• v.25 no.2
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• pp.376-380
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• 2021

In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to existing ESD protection circuits. Furthermore, the variation of electrical properties was verified using the design variable D1. Simulation results confirm that the proposed ESD protective circuit has higher holding voltage properties and bidirectional discharge properties compared to conventional ESD protective circuits. We validate the electrical properties with post-design TLP measurements using Samsung's 0.13um BCD process. And we verify that the proposed ESD protection circuit in this paper is well suited for high voltage applications in that it has a latch-up immunity due to improved holding voltage through optimization of design variables.

• Journal of IKEEE
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• v.17 no.2
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• pp.208-213
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• 2013

In this paper, we proposed the novel SCR-based ESD protection circuit with high holding voltage for power clamp. In order to increase the holding voltage, the floating p+ and n+ to n-well and p-well, respectively, in the conventional SCR. The resulting increase of the holding voltage of the our proposed ESD circuit enables the high latch-up immunity. The electrical characteristics including ESD robustness of the proposed ESD circuit have been simulated using Synopsys TCAD simulator. According to the simulation result, the proposed device has higher holding voltage of 4.98 V than that of the conventional SCR protection circuit. Moreover, it is confirmed that the device could have the holding voltage of maximum 13.26 V with the size variation of floated diffusion area.

• Journal of IKEEE
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• v.25 no.2
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• pp.280-284
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• 2021

In this paper, a new ESD protection circuit is proposed to improve the snapback characteristics. The proposed a new structure ESD protection circuit applying the conventional SCR structural change and stack structure. The electrical characteristics of the structure using penta-well and double trigger were analyzed, and the trigger voltage and holding voltage were improved by applying the stack structure. The electron current and total current flow were analyzed through the TCAD simulation. The characteristics of the latch-up immunity and excellent snapback characteristics were confirmed. The electrical characteristics of the proposed ESD protection circuit were analyzed through HBM modeling after forming a structure through TCAD simulator.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.731-734
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.88-97
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• 1993

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

• Journal of IKEEE
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• v.22 no.1
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• pp.80-86
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• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• Journal of IKEEE
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• v.17 no.3
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• pp.378-384
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• 2013

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

• ETRI Journal
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• v.39 no.5
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.