Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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The Design of SCR-based Whole-Chip ESD Protection with Dual-Direction and High Holding Voltage

양 방향성과 높은 홀딩전압을 갖는 사이리스터 기반 Whole-Chip ESD 보호회로

  • Song, Bo-Bae (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Han, Jung-Woo (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Nam, Jong-Ho (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Choi, Yong-Nam (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Koo, Yong-Seo (Dept. of Electronics and Electrical Engineering, Dankook University)
  • Received : 2013.09.13
  • Accepted : 2013.09.26
  • Published : 2013.09.30
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Abstract

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

본 논문에서는 높은 홀딩 전압을 갖는 SCR 기반의 파워 클램프용 ESD 보호회로와 whole-chip ESD 보호를 위한 양 방향성 ESD 보호회로를 제안하였다. 측정 결과, 파워 클램프의 경우 N/P-웰과 P-drift 영역의 길이의 변화에 따른 홀딩 전압의 증가를 확인하였으며 I/O의 경우 5V의 트리거 전압과 3V의 홀딩 전압을 확인하였다. 일반적인 whole-chip ESD 보호회로와 달리, VDD-VSS 모드 뿐만 아니라 PD, ND, PS, NS의 ESD stress mode의 방전 경로를 제공하여 효과적인 보호를 제공하며 최대 HBM 8kV, MM 400V의 감내특성을 가진다. 따라서 제안된 whole-chip ESD 보호회로는 2.5V~3.3V의 공급전원을 가지는 application에 적용 가능하다.

Keywords

References

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