Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design of ESD Protection Circuit with improved Snapback characteristics Using Stack Structure

스텍 구조를 이용한 향상된 스냅백 특성을 갖는 ESD 보호회로 설계

  • Received : 2021.05.18
  • Accepted : 2021.05.26
  • Published : 2021.06.30
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Abstract

In this paper, a new ESD protection circuit is proposed to improve the snapback characteristics. The proposed a new structure ESD protection circuit applying the conventional SCR structural change and stack structure. The electrical characteristics of the structure using penta-well and double trigger were analyzed, and the trigger voltage and holding voltage were improved by applying the stack structure. The electron current and total current flow were analyzed through the TCAD simulation. The characteristics of the latch-up immunity and excellent snapback characteristics were confirmed. The electrical characteristics of the proposed ESD protection circuit were analyzed through HBM modeling after forming a structure through TCAD simulator.

본 논문에서는 스냅백 특성을 개선시키기 위해 일반적인 SCR의 구조적 변경 및 Stack 기술을 적용한 새로운 구조의 ESD 보호회로를 제안한다. 펜타-웰과 더블 트리거를 이용한 구조에 대한 전기적 특성을 분석하고 Stack 구조를 적용해 트리거 전압과 홀딩 전압을 개선하였다. 시뮬레이션을 통한 전자 전류와 총 전류 흐름을 분석 하였다. 이를 통해 레치-업 면역 특성과 우수한 홀딩전압 특성을 확인 하였다. 제안된 ESD 보호회로의 전기적 특성은 TCAD 시뮬레이터를 통해 구조를 형성하고 HBM 모델링을 통해 분석 하였다.

Keywords

Acknowledgement

This research was supported by Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Ministry of Trade, Industry & Energy ('20009972', The development of High efficient low power circuit element and SoC for the light weight edge device)

References

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