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http://dx.doi.org/10.5573/JSTS.2017.17.3.401

Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs  

Choi, Jin-Young (Dept. of Electronic & Electrical Engineering, Hongik University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.17, no.3, 2017 , pp. 401-410 More about this Journal
Abstract
In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.
Keywords
ESD protection; diode protection device; mixed-mode simulation; parasitic bipolar transistor; RF ICs;
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  • Reference
1 P. Leroux and M. Steyaert,. "High-performance 5.2GHz LNA with On-chip Inductor to Provide ESD Protection," Electronics Letters, vol. 37, pp. 467-469, Mar. 2001.   DOI
2 C.-T. Yeh, M.-D. Ker, and Y. C. Liang, "Optimization of Layout Style of ESD Protection Diode for Radio-frequency Front-end and High-speed I/O Interface Circuits," IEEE Trans. Device and Materials Reliability, vol. 10, pp. 238-246, June 2010.   DOI
3 M.-T. Yang et al., "BSIM4-based Lateral Diode Model for LNA Co-designed with ESD Protection Circuit," 11th Int. Symp. on Quality Electronic Design, 22-24, Mar. 2010, pp. 87-91.
4 T. Au and M. Syrzycki, "Investigation of STI Diodes as Electrostatic Discharge (ESD) Protection Devices in Deep Submicron (DSM) CMOS Process," 26th IEEE CCECE, 5-8, May 2013, pp. 1-5.
5 K. Bhatia, N. Jack, and E. Rosenbaum, "Layout Optimization of ESD Protection Diodes for High-frequency I/Os," IEEE Trans. Device and Materials Reliability, vol. 9, no. 3, 465-475, Sept. 2009.   DOI
6 J. Y. Choi,."On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device," Circuits and Systems, vol. 7, pp. 2286-2295, July 2016.   DOI
7 H. Feng, et al., "A mixed-mode ESD Protection Circuit Simulation-design methodology," IEEE J. Soilid-State Circuits, vol. 38, pp. 995-1006, June 2003.   DOI
8 B. Fankhauser, and B. Deutschmann, "Using Device Simulations to Optimize ESD Protection Circuits," IEEE EMC Symp., 9-13, Aug. 2004, pp.963-968.
9 J. Y. Choi, "A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode," Communications and Network, vol. 2, pp. 11-25, Feb. 2010.   DOI
10 ATLAS II Framework, Version 5.10.2.R, Silvaco International, 2005.
11 Z. H. Liu, et al., "A Comparative Study of the Effect of Dynamic Stressing on High-field Endurance and Stability of Reoxidized-nitrided, Fluorinated and Conventional Oxides," IEEE IEDM, Tech. Digest, 8-11, Dec. 1991, pp. 723-726.