• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.673-681
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• 2014

In this paper, a novel low specific on-resistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped $P^+$ region which is connected to the P-top layer in the drift region. The $P^+$ region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel $P^+P$-top device also present cost efficiency due to the fact that the $P^+$ region can be fabricated together with the P-type body contact region without any additional mask.

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2008년도 한국우주과학회보 제17권2호
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• pp.30.4-31
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• 2008

Formation of longitudinally wave-like plasma density structure in the low-latitude F region is now a well-known phenomenon from the extensive studies in recent years. Observations of plasma density from multiple satellites have shown that the locations of the crests of the plasma density that are seen to be stationary during daytime are shifted after sunset. This phenomenon has been understood to be caused by eastward drift of the ionosphere at night. However, the eastward drift velocity of the ionosphere after sunset is not sufficiently large enough to explain the day-night difference in the longitudinal density structure. The just after sunset and the nighttime ionospheric morphologymay be affected by this drift after sunset. In this study, we will investigate the temporal variation of the phase of the longitudinal density structure and vertical plasma drift by analyzing the ROCSAT-1, TIMED/GUVI, and DMSP data and verify the role of the vertical drift after sunset in the change of the phase of the longitudinal density structure.

• 전자공학회논문지A
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• 제33A권7호
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• ETRI Journal
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• 제26권1호
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• pp.7-13
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• 2004

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.686-694
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• 2014

A power semiconductor device, usually used as a switch or rectifier, is very significant in the modern power industry. The power semiconductor, in terms of its physical properties, requires a high breakdown voltage to turn off, a low on-state resistance to reduce static loss, and a fast switching speed to reduce dynamic loss. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. Although the low doping concentration in the drift region increases the breakdown voltage, the on-state resistance that is increased along with it makes the static loss characteristic deteriorate. On the other hand, although the high doping concentration in the drift region reduces on-state resistance, the breakdown voltage is decreased, which limits the scope of its applications. This addresses the fact that breakdown voltage and on-state resistance are in a trade-off relationship with a parameter of the doping concentration in the drift region. Such a trade-off relationship is a hindrance to the development of power semiconductor devices that have idealistic characteristics. In this study, a novel structure is proposed for the Insulated Gate Bipolar Transistor (IGBT) device that uses conductivity modulation, which makes it possible to increase the breakdown voltage without changing the on-state resistance through use of a P-floating layer. More specifically in the proposed IGBT structure, a P-floating layer was inserted into the drift region, which results in an alleviation of the trade-off relationship between the on-state resistance and the breakdown voltage. The increase of breakdown voltage in the proposed IGBT structure has been analyzed both theoretically and through simulations, and it is verified through measurement of actual samples.

• Journal of Information Processing Systems
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• 제15권6호
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• pp.1350-1364
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• 2019

The ice damage occurs frequently in cold and dry region of western China in winter ice period and spring thaw period. In the drift ice condition, it is easy to form different extrusion force or impact force to damage tunnel lining, causing project failure. The failure project could not arrive the original planning and construction goal, giving rise to the water allocation pressure which influences diversion irrigation and farming production in spring. This study conducts the theoretical study on contact-impact algorithm of drift ices crashing diversion tunnel based on the symmetric penalty function in finite element theory. ANSYS/LS-DYNA is adopted as the platform to establish tunnel model and drift ice model. LS-DYNA SOLVER is used as the solver and LS-PREPOST is used to do post-processing, analyzing the damage degrees of drift ices on tunnel. Constructing physical model in the experiment to verify and reveal the impact damage mechanism of drift ices on diversion tunnel. The software simulation results and the experiment results show that tunnel lining surface will form varying degree deformation and failure when drift ices crash tunnel lining on different velocity, different plan size and different thickness of drift ice. The researches also show that there are damages of drift ice impact force on tunnel lining in the thawing period in cold and dry region. By long time water scouring, the tunnel lining surfaces are broken and falling off which breaks the strength and stability of the structure.

• ETRI Journal
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• 제36권5호
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• 대한전자공학회논문지SD
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• 제39권10호
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• pp.9-15
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• 2002

드리프트 영역에서의 속도 오버슈트 효과를 이용하여 서브밀리미터파 주파수 영역에서 동작하는 새로운 주행 시간 소자를 제안한다. 이 소자를 속도 오버슈트 주행 시간(VOTT) 다이오드라 명명한다. 이 소자는 캐리어 주입 메커니즘으로 빠르게 이루어지는 이종구조 터널링을 이용하며, 속도 오버슈트 효과를 최적화하기 위하여 짧은 드리프트 영역을 갖는다. 변환효율을 증대시키기 위하여 에너지 대역 간극을 경사시키는 방법으로 드리프트영역을 설계한다. 모의실험결과에 따르면 이 소자는 THz 영역에서 동작하리라 기대된다.

• 한국전기전자재료학회논문지
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• 제18권7호
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• pp.667-674
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• 2005

In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.

• 전자공학회논문지A
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• 제31A권12호
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• pp.100-105
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• 1994

SOI(Silicon-On-Insulator) pn 다이오드의 최적 수평길이($L_{dr}$)와 항복전압에 대한 해석적인 표현식을 n' 츠리프트 영역의 농도 및 두께, 매몰 산화막 두께의 함수로 유도하였다. 최적($L_{dr}$은 n'n접합의 수직 방향전계에 의한 항복전압과 n'np'접합으 수평방향 전계에 의한 항복전압이 같다는 조건으로부터 유도하였다. 해석적 표현식의 결과는 PISCESII를 사용한 시뮬레이션 결과와 잘 일치하였다.