• 한국전기전자재료학회논문지
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• 제33권1호
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• pp.78-82
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• 2020

In this study, MOSFETs fabricated on Si-doped, MBE-grown β-Ga₂O₃ are demonstrated. A Si-doped Ga₂O₃ epitaxial layer was grown on a Fe-doped, semi-insulating 1.5 cm × 1 cm Ga₂O₃ substrate using molecular beam epitaxy (MBE). The fabricated devices are circular type MOSFETs with a gate length of 3 ㎛, a source-drain spacing of 20 ㎛, and a gate width of 523 ㎛. The device exhibited a good pinch-off characteristic, a high on-off drain current ratio of approximately 2.7×10⁹, and a high breakdown voltage of 1,080 V, which demonstrates the potential of Ga₂O₃ for power device applications including electric vehicles, railways, and renewable energy.

• Geomechanics and Engineering
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• 제7권5호
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• pp.525-537
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• 2014

The typical design of ground improvement with prefabricated vertical drains (PVD) and surcharge preloading involves a series of deterministic analyses using averaged or mean soil properties for the various combination of the PVD spacing and surcharge preloading height that would meet the criteria for minimum consolidation time and required degree of consolidation. The optimum design combination is then selected in which the total cost of ground improvement is a minimum. Considering the variability and uncertainties of the soil consolidation parameters, as well as considering the effects of soil disturbance (smear zone) and drain resistance in the analysis, this study presents a stochastic cost optimization of ground improvement with PVD and surcharge preloading. Direct Monte Carlo (MC) simulation and importance sampling (IS) technique is used in the stochastic analysis by limiting the sampled random soil parameters within the range from a minimum to maximum value while considering their statistical distribution. The method has been verified in a case study of PVD improved ground with preloading, in which average results of the stochastic analysis showed a good agreement with field monitoring data.

• 한국전기전자재료학회논문지
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• 제32권3호
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1706-1711
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• 1989

Unit processes for the fabrication of HEMT(high electron mobility transistor)was studied and the optimum conditions of them were applied to the fabrifcation of a discrete HEMT device. The HEMT with a nominal gate-source spacing of 3.6\ulcorner and a gate length of 2.8\ulcorner showed a transconductance of 46.1mS/mm and a threshold voltage of -0.29V. A source-drain voltage of 2.0V for a saturation current of 35mA/mm was achieved.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

• 아시안잔디학회지
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• 제17권4호
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• pp.155-163
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• 2003

우리나라 1인당 도시공원 면적은 6.46$m^2$로 도시녹지공간이 매우 부족하여 도심 콘크리트 옥상의 녹화는 거주자에게 산책, 휴식, 운동 및 레크리에이션 공간으로 활용될 수 있을 것이다. 본 연구는 도시 옥상녹화에 적합한 지반, 점적 관수 및 잔디초종을 선발하고자 실험을 실시하였다. 옥상잔디 조성에 적합한 혼합토를 찾기 위해 하중과 배수효율을 고려하여 토양개량재와 배수구조를 달리한 네 개 조합의 잔디 지반구조를 설치하였다. 또한 자동 점적 관수시스템의 최적 조건을 구명하기 위해 주관 간격(50cm, 100cm)과 점적기 간격(15cm, 20cm, 30cm, 50cm, 100cm)을 달리 처리하였다. 잔디종류를 선정하기 위해 버뮤다그래스 '건우', 세엽 한국들잔디 '건희'와 Kentucky bluegrass, Perennial ryegrass 와 Tall fescue 한지형잔디 혼파 두 조합을 식재 후 잔디의 생육상태를 비교하였다. 토양개량재의 입도 분석 결과 펄라이트와 질석 입자 입경은 98%가 4.75∼l.75mm로 균일한 입도를 나타내었다. 그러나 피트모스는 다량의 섬유질 때문에 4.75mm의 채를 통과하지 못하는 비율이 60%로 매우 높았다. 또한 포화수분하의 토양개량재 별 하중을 조사한 결과 건조 시 펄라이트의 1$\ell$ 당 무게는 0.2kg로 매우 가벼웠으며 포화수분 하에서 무게증가는 1.66 배로 작게 나타났다. 반면 질석과 피트모스의 경우 건조 시 각각 0.1kg, 0.2kg으로 매우 가벼웠으나 포화수분 하에서 3.5배 이상으로 무게가 많이 증가하였다. 혼합토 처리별 하중은 처리구 모두 200kg/$m^2$ 이하로서 일반 학교 옥상의 제한하중 범위 내에 속하였다. 특히 스티로폼 배수층이 포함된 Mixture III은 139.2kg/$m^2$로 가장 가벼웠다. 또한 혼합토에 따른 잔디품질은 스티로폼 배수층이 있는 Mixture III와 IV에서 우수하게 나타났다. 옥상 녹화용 점적 관수시설의 균일한 전면관 수를 위해 주관의 배치 간격은 50cm 이내가 적합한 것으로 나타났다. 특히 한지형 잔디는 100cm 이상의 주관 폭에서 건조로 고사 현상이 나타났으며 초기 관수효율은 점적기의 간격이 짧을수록 잔디 생육이 우수하였으나 조성시간이 경과할수록 점적기의 간격은 50cm에서 잔디생육이 우수하였다. 자동 타이머에 의해 조절된 관수 간격은 1일 1회 관수 된 처리구의 잔디 품질이 우수한 것으로 나타났다. 잔디 종류는 난지형잔디에서 혼합토 종류 및 모든 관수 시설 처리서 우수한 생육을 나타내었으나 한지형 잔디는 관수시설에 따라 생육이 차이가 현저하게 나타났다. 따라서 한지형 잔디로 옥상 조경 시 적합 혼합토 및 관수 시설의 선정에 유의하여야 할 것으로 판단된다. 또한 버뮤다그래스는 중부지역의 경우 월동력이 낮으므로 온도변화가 심한 옥상 콘크리트 환경에서 버뮤다그래스 '건우'의 월동에 대한 연구가 지속되어야 할 것으로 판단된다.

• 대한전자공학회논문지SD
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• 제42권3호
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• pp.1-8
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• 2005

본 논문에서는 $0.1\;{\mu}m$ 이하의 게이트 길이를 갖는 MHEMT의 DC 및 RF 특성을 상용 시뮬레이터인 ISE-TCAD tool을 이용하여 결과를 고찰하였다. 이후 MHEMT의 게이트 길이와, 소스-드레인 간격 및 채널 두께를 변화시켜 가면서 소자의 수평, 수직 Scaling효과가 소자 특성에 미치는 영향을 비교하였으며, 게이트 길이 $(L_g)$가 $0.1\;{\mu}m$ 이하로 감소함에 따라 $g_{m,max}$가 같이 감소하는 현상에 대해서 논의해 보았다. 또한 이 현상을 가지고 소자의 횡적, 종적 파라미터의 scaling 효과에 대한 모델을 제시 했다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.675-678
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• 2003

We studied the electrical characteristics of pentacene-based organic field-effect transistors (FETs) with polymethyl methacrylate (PMMA) or poly-4-vinylphenol (PVP) as the gate insulator. PMMA or PVP was spin-coated on the indium tin oxide glass substrate that serves as gate electrodes. The source-drain current dependence on the gate voltage shows the FET characteristics of the hole accumulation type. The transistor with PVP shows a higher field-effect mobility of 0.14 $cm^{2}/Vs$ compared with 0.045 $cm^{2}/Vs$ for the transistor with PMMA. The atomic force microscope (AFM) images indicate that the grain size of the pentacene on PVP is larger than that on PMMA. X-ray diffraction (XRD) patterns for the pentacene deposited on PVP exhibit a new Bragg reflection at $19.5{\pm}0.2^{\circ}$, which is absent for the pentacene on PMMA. This peak corresponds to the flat-lying pentacene molecules with less intermolecular spacing.

• 한국지반공학회논문집
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• 제16권2호
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• pp.61-70
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• 2000

When clay foundations of embankments are treated with vertical drain, essentially, the strain occurs to vertical direction but the water flow is radial. The initial horizontal permeability and its variation with the vertical compression are key parameters for the choice of the type of drains, their spacing, and affect to the cost of the project. In this study, CRS consolidation test is performed to investigate the anisotropic characteristics of decomposed mudstone soil and direct permeability test is performed on the same specimens. The results of testing show that Ch is larger than Cv. specially, the Cv - $\sigma$v relationship for a soil sample is viewed from three different curve segments corresponding to overconsolidated, transition and normally consolidated states. The anisotropic ratio, rk(kh/kv) is 2.19. Coefficient of permeability in normally consolidated state is related to its void ratio and permeability parameter n. C can be determined from a linear plot of log[k(1+e)] versus log e. The slope, n, of graphs is the same, whereas the vertical intercept, log C, seems to vary somewhat for anisotropic.

• 한국전기전자재료학회논문지
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• 제17권9호
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• pp.911-915
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• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.