• 한국재료학회지
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• 제13권6호
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• 한국세라믹학회지
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• 제38권10호
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• 설비공학논문집
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• 제13권5호
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• pp.356-367
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• 2001

A numerical analysis on branch type sparger in drain tank for depressurization is performed to investigate the flow characteristics due to the change of design factor. As the result of this study, sparger\\`s flow resistance coefficient(K) is 3.53 at the present design condition when engineering margin for surface roughness is considered as 20%, and flow ratio into branch pipe ($Q_s/Q_i$) is 0.41. The correlation for calculating flow resistance coefficients as design factor is presented. Flow resistance coefficient is increased as section area ratio of branch pipe for main pipe and outlet nozzle diameter of main pipe decreasing, but the effects of branch angle and inlet flow rate of main pipe are small. As the change rate of ($Q_s/Q_i$)becomes larger, the change rate of flow resistance coefficient increases. The rate of pressure loss has the largest change as section area ratio changing. The condition of maximum flow resistance in sparger is when the outlet nozzle diameter ratio of main pipe ($D_e/D_i$) is 0.167, the section area ratio ($A_s/A_i$) is 0.1 and the branch angle ($\alpha$) is 55^{\circ}$.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2009년도 세계 도시지반공학 심포지엄
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• pp.449-456
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• 2009

As soft grounds have complex engineering properties that the load bearing capacity is low and high compressibility, it needs to solve this problems prior to structures are constructed by the method of improvement of soft ground. Generally, the sand mat is used to as a horizontal drain material and loading base for soft ground improvement work. However, as the natural environment can be damaged by sand pickings of large quantity and the volume which is enormous and an amount of demanded sand is increased, it is state of short in supply. This paper presents the result of field experimental test to use Precious Slag Ball to solve these issues instead of sand mat as the replacing material. This study evaluated the performance of Precious Slag Ball as a sand mat in terms of discharge capacity, settlement, and settlement through the K-Embank program.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• Journal of Power Electronics
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• 제18권6호
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

• 전자공학회논문지
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• 제52권4호
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• pp.49-55
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• 2015

기존의 BSIM4 모델과 다이오드를 사용한 BSIM4 Macro 모델의 바이어스 종속 게이트-드레인 오버렙 캐패시턴스 $C_{gdo}$ 시뮬레이션의 부정확성에 대하여 자세히 분석하였다. 이러한 Macro 모델은 기존의 BSIM4 모델보다 더 정확하지만 선형영역에서 사용될 수 없음을 발견하였다. 기존 모델들의 부정확성을 제거하기 위해서 물리적인 바이어스 종속 $C_{gdo}$ 모델 방정식을 사용한 새로운 BSIM4 Macro 모델을 제안하였고 전체 바이어스 영역에서 유효함을 입증하였다.

• STI Policy Review
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• 제5권2호
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• pp.43-64
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• 2014

Korea has pursued an aggressive policy of inviting more foreign-born students to its universities since the late 1990s in the wake of the globalization of education markets and its changing demographic structure. While increasingly more students from Asia come to Korea for study, more than half of the graduates return home upon graduation. Given the issues of brain drain, brain circulation, and knowledge transfer that are raised by such a high return rate, this paper examines the factors that frame the foreign students' decision on their post-graduation careers. By analyzing survey data, we report that Asian students majoring in science, technology, engineering, and mathematics (STEM) are more likely to return than non-STEM majors. This suggests that Korea's aggressive policies of inviting foreign-born students have contributed to brain circulation and knowledge transfer between Korea and the other Asian countries. We also find that scholarships from Korean sources and positive attitudes toward Korean culture and life increase their inclination to stay in the country upon graduation. These findings, however, raise more questions than answers, since it becomes obvious that their post-graduation decisions are highly affected by what Korea as a society provides.

• 융합정보논문지
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• 제11권11호
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• pp.159-165
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• 2021

본 삼차원 선택적 산화를 이용하여 20 nm 수준의 핀 폭과 점진적으로 증가된 소스/드레인 확장 영역을 갖는 핀 채널을 벌크 실리콘 기판에 제작하였다. 제안된 기법을 이용하여 삼차원 소자를 제작하기 위한 공정기법 및 단계를 상세히 설명하였다. 삼차원 소자 시뮬레이션을 통해, 제안된 소자의 주요 특징과 특성을 기존 FinFET 및 벌크 FinFET 소자와 비교하였다. 제안된 삼차원 선택적 산화 방식의 핀 채널 MOSFET는 기존의 소자들과 비교하여 더 큰 구동 전류, 더 높은 선형 트랜스컨덕턴스, 더 낮은 직렬 저항을 가지며, 거의 유사한 수준의 소형화 특성을 보이는 것을 확인하였다.

• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2021년도 학술발표회
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• pp.146-146
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• 2021

A contamination event occurring in water distribution networks (WDNs) needs to be handled with the appropriate mitigation strategy to protect public health safety and ensure water supply service continuation. Typically the mitigation phase consists of contaminant sensing, public warning, network inspection, and recovery. After the contaminant source has been detected and treated, contaminants still exist in the network, and the contaminated water should be flushed out. The recovery period is critical to remove any lingering contaminant in a rapid and non-detrimental manner. The contaminant flushing can be done in several ways. Conventionally, the opening of hydrants is applied to drain the contaminant out of the system. Relying on advanced information and communication technology (ICT) on WDN management, warning and information can be distributed fast through electronic media. Water utilities can inform their customers to participate in the contaminant flushing by opening and closing their house faucets to drain the contaminated water. The household draining strategy consists of determining sectors and timeslots of the WDN users based on hydraulic simulation. The number of sectors should be controlled to maintain sufficient pressure for faucet draining. The draining timeslot is determined through hydraulic simulation to identify the draining time required for each sector. The effectiveness of the strategy is evaluated using three measurements, such as Wasted Water (WW), Flushing Duration (FD), and Pipe Erosion (PE). The optimal draining strategy (i.e., group and timeslot allocation) in the WDN can be determined by minimizing the measures.