• Korean Journal of Materials Research
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• v.13 no.6
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.13 no.5
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• pp.356-367
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• 2001

A numerical analysis on branch type sparger in drain tank for depressurization is performed to investigate the flow characteristics due to the change of design factor. As the result of this study, sparger\\`s flow resistance coefficient(K) is 3.53 at the present design condition when engineering margin for surface roughness is considered as 20%, and flow ratio into branch pipe ($Q_s/Q_i$) is 0.41. The correlation for calculating flow resistance coefficients as design factor is presented. Flow resistance coefficient is increased as section area ratio of branch pipe for main pipe and outlet nozzle diameter of main pipe decreasing, but the effects of branch angle and inlet flow rate of main pipe are small. As the change rate of ($Q_s/Q_i$)becomes larger, the change rate of flow resistance coefficient increases. The rate of pressure loss has the largest change as section area ratio changing. The condition of maximum flow resistance in sparger is when the outlet nozzle diameter ratio of main pipe ($D_e/D_i$) is 0.167, the section area ratio ($A_s/A_i$) is 0.1 and the branch angle ($\alpha$) is 55^{\circ}$.

• Proceedings of the Korean Geotechical Society Conference
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• 2009.09a
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• pp.449-456
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• 2009

As soft grounds have complex engineering properties that the load bearing capacity is low and high compressibility, it needs to solve this problems prior to structures are constructed by the method of improvement of soft ground. Generally, the sand mat is used to as a horizontal drain material and loading base for soft ground improvement work. However, as the natural environment can be damaged by sand pickings of large quantity and the volume which is enormous and an amount of demanded sand is increased, it is state of short in supply. This paper presents the result of field experimental test to use Precious Slag Ball to solve these issues instead of sand mat as the replacing material. This study evaluated the performance of Precious Slag Ball as a sand mat in terms of discharge capacity, settlement, and settlement through the K-Embank program.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.49-55
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• 2015

The inaccuracy of the bias-dependent gate-drain overlap capacitance $C_{gdo}$ simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. It is found that the accuracy of the macro model is better than of the BSIM4. However, the macro model cannot be used in the linear region. In order to remove the inaccuracy of the conventional models, a new BSIM4 macro model with a physical bias-dependent $C_{gdo}$ equation is proposed and its accuracy is validated in the full bias range.

• STI Policy Review
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• v.5 no.2
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• pp.43-64
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• 2014

Korea has pursued an aggressive policy of inviting more foreign-born students to its universities since the late 1990s in the wake of the globalization of education markets and its changing demographic structure. While increasingly more students from Asia come to Korea for study, more than half of the graduates return home upon graduation. Given the issues of brain drain, brain circulation, and knowledge transfer that are raised by such a high return rate, this paper examines the factors that frame the foreign students' decision on their post-graduation careers. By analyzing survey data, we report that Asian students majoring in science, technology, engineering, and mathematics (STEM) are more likely to return than non-STEM majors. This suggests that Korea's aggressive policies of inviting foreign-born students have contributed to brain circulation and knowledge transfer between Korea and the other Asian countries. We also find that scholarships from Korean sources and positive attitudes toward Korean culture and life increase their inclination to stay in the country upon graduation. These findings, however, raise more questions than answers, since it becomes obvious that their post-graduation decisions are highly affected by what Korea as a society provides.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.146-146
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• 2021

A contamination event occurring in water distribution networks (WDNs) needs to be handled with the appropriate mitigation strategy to protect public health safety and ensure water supply service continuation. Typically the mitigation phase consists of contaminant sensing, public warning, network inspection, and recovery. After the contaminant source has been detected and treated, contaminants still exist in the network, and the contaminated water should be flushed out. The recovery period is critical to remove any lingering contaminant in a rapid and non-detrimental manner. The contaminant flushing can be done in several ways. Conventionally, the opening of hydrants is applied to drain the contaminant out of the system. Relying on advanced information and communication technology (ICT) on WDN management, warning and information can be distributed fast through electronic media. Water utilities can inform their customers to participate in the contaminant flushing by opening and closing their house faucets to drain the contaminated water. The household draining strategy consists of determining sectors and timeslots of the WDN users based on hydraulic simulation. The number of sectors should be controlled to maintain sufficient pressure for faucet draining. The draining timeslot is determined through hydraulic simulation to identify the draining time required for each sector. The effectiveness of the strategy is evaluated using three measurements, such as Wasted Water (WW), Flushing Duration (FD), and Pipe Erosion (PE). The optimal draining strategy (i.e., group and timeslot allocation) in the WDN can be determined by minimizing the measures.