• Title/Summary/Keyword: Drain current

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Design and Evaluation of Cascode GaN FET for Switching Power Conversion Systems

  • Jung, Dong Yun;Park, Youngrak;Lee, Hyun Soo;Jun, Chi Hoon;Jang, Hyun Gyu;Park, Junbo;Kim, Minki;Ko, Sang Choon;Nam, Eun Soo
    • ETRI Journal
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    • v.39 no.1
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    • pp.62-68
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    • 2017
  • In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.

Effects of Pentacene Thickness and Source/Drain Contact Location on Performance of Penatacene TFT (펜타센 박막의 두께와 전극위치가 펜타센 TFT 성능에 미치는 영향)

  • 이명원;김광현;송정근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1001-1007
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    • 2002
  • In this paper we analyzed the effects of pentacene thickness and the location of source/drain contacts on the performance of pentacene TFT Above a certain thickness of pentacene thin film the pentacene grain was turned from the thin film phase into the bulk phase, resulting in degrading the crystallinity and then performance as well. For the top contact structure in which source/drain contacts are located above pentacene film, the contact resistance decreased comparing with the bottom contact structure. However, the leakage current in the off-state became large and then the related parameters such as on/off current ratio were deteriorated. We found that the thickness of around 300$\AA$-700$\AA$ was suitable, and that the bottom contact was more feasible for hig Performance pentacene OTFT.

Simulation Study on the Breakdown Characteristics of InGaAs/InP Composite Channel MHEMTs with an InP-Etchstop Layer (InP 식각정지층을 갖는 MHEMT 소자의 InGaAs/InP 복합 채널 항복 특성 시뮬레이션)

  • Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.12 no.4
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    • pp.21-25
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    • 2013
  • This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation

  • Vanitha, P.;Balamurugan, N.B.;Priya, G. Lakshmi
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.585-593
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    • 2015
  • In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

Effect of electron-beam irradiation on leakage current of AlGaN/GaN HEMTs on sapphire

  • Oh, Seung Kyu;Song, Chi Gyun;Jang, Taehoon;Kwak, Joon Seop
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.617-621
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    • 2013
  • This study examined the effect of electron-beam (E-beam) irradiation on the electrical properties of n-GaN, AlGaN and AlGN/GaN structures on sapphire substrates. E-beam irradiation resulted in a significant decrease in the gate leakage current of the n-GaN, AlGaN and HEMT structure from $4.0{\times}10^{-4}A$, $6.5{\times}10^{-5}A$, $2.7{\times}10^{-8}A$ to $7.7{\times}10^{-5}A$, $7.7{\times}10^{-6}A$, $4.7{\times}10^{-9}A$, respectively, at a drain voltage of -10V. Furthermore, we also investigated the effect of E-beam irradiation on the AlGaN surface in AlGaN/GaN heterostructure high electron mobility transistors(HEMTs). The results showed that the maximum drain current density of the AlGaN/GaN HEMTs with E-beam irradiation was greatly improved, when compared to that of the AlGaN/GaN HEMTs without E-beam irradiation. These results strongly suggest that E-beam irradiation is a promising method to reduce leakage current of AlGaN/GaN HEMTs on sapphire through the neutralization the trap.

Design of Current-Mode Class-D 900 MHz RF Power Amplifier Using Inverse Class-F Technology (Inverse Class-F 기법을 이용한 900 MHz 전류 모드 Class-D RF 전력 증폭기 설계)

  • Kim, Young-Woong;Lim, Jong-Gyun;Kang, Won-Shil;Ku, Hyun-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.12
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    • pp.1060-1068
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    • 2011
  • In this paper, Current-Mode Class-D(CMCD) RF Power Amplifier(PA) is designed and implemented at 900 MHz. Conventional CMCD PA has output parallel resonator to reconstruct a fundamental frequency component of the output signal. However the resonator can be removed by connecting inverse class-F PAs because even-harmonic components can be removed by CMCD PA's push-pull structure. Using load-pull, inverse class-F PA with GaN transistors is designed, and CMCD PA with the inverse class-F PA is implemented. The CMCD PA has 64.5 % drain efficiency, 34.2 dBm output power. Comparing with the drain efficiency of a CMCD PA with parallel resonator, the CMCD with the inverse class-F technology has 13.6 % improved drain efficiency.

Degradation Characteristics by Hot Carrier Injection of nchannel MOSFET with Gate- $n^{-}$S/D Overlapped Structure (게이트와 $n^{-}$소스/드레인 중첩구조를 갖는 n 채널 MOSFET의 핫캐리어 주입에의한 소화특성)

  • 이대우;이우일
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.36-45
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    • 1993
  • The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

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Lateral Electric Field Model and Degradation Mechanism of surface-Channel PMOSFET's (SC PMOSFET의 수평 전개 모델과 노쇠화 메카니즘)

  • 양광선;박종태;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.1
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    • pp.54-60
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    • 1994
  • In this paper, we present the analytical models for the change of the lateral electric field distribution and the velocity saturation region length with the electron trapping of stressed SC-PMOSFET in the saturation region. To derive the hot-electron-induced lateral electric field of stressed SC-PMOSFET. Ko's pseudo two dimensional box model in the saturation region which illustrates the analysis of the velocity saturation region is modified under the condition of electron trapping in the oxide near the drain region. From the results, we have the following lateral electric field in the y-direction, that is, E(y) ES1satT.cosh(y/l) qNS1tT.sinh(y/l)/lCox. It is shown that the trapped electrons influence the field in the drain region. decreasing the lateral electric field. Calculated velocity saturaion length increases with the trapped electrons. increasing the drain current of stressed SCPMOSFET. This results well explain the HEIP phenomenon of PMOSFET's.

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Rabrication of 4.7 V Operation GaAs power MESFETs and its characteristics at 900 MHz (900MHz 대역 4.7 V 동작 전력소자 제작 및 특성)

  • 이종람;김해천;문재경;권오승;이해권;황인덕;박형무
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.71-78
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    • 1994
  • We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

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Analytical Thermal Noise Model of Deep-submicron MOSFETs

  • Shin, Hyung-Cheol;Kim, Se-Young;Jeon, Jong-Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.3
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    • pp.206-209
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    • 2006
  • This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deep-submicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.