Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Effects of Pentacene Thickness and Source/Drain Contact Location on Performance of Penatacene TFT

펜타센 박막의 두께와 전극위치가 펜타센 TFT 성능에 미치는 영향

  • 이명원 (동아대학교 전기전자컴퓨터공학부) ;
  • 김광현 (동아대학교 전기전자컴퓨터공학부) ;
  • 송정근 (동아대학교 전기전자컴퓨터공학부)
  • Published : 2002.12.01
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Abstract

In this paper we analyzed the effects of pentacene thickness and the location of source/drain contacts on the performance of pentacene TFT Above a certain thickness of pentacene thin film the pentacene grain was turned from the thin film phase into the bulk phase, resulting in degrading the crystallinity and then performance as well. For the top contact structure in which source/drain contacts are located above pentacene film, the contact resistance decreased comparing with the bottom contact structure. However, the leakage current in the off-state became large and then the related parameters such as on/off current ratio were deteriorated. We found that the thickness of around 300$\AA$-700$\AA$ was suitable, and that the bottom contact was more feasible for hig Performance pentacene OTFT.

된 논문에서는 펜타센을 활성층으로 사용하는 유기박막트랜지스터(OTFT)의 펜타센의 두께, 그리고 소오스 및 드레인 전극의 위치에 따른 소자의 성능 변화에 대하여 연구하였다. 펜타센 박막의 두께가 증가하면 그레인 상태가 박막상태에서 벌크상태로 변화하면서 결정도가 악화되어 성능이 열화하였고, 소오스와 드레인 전극을 펜타센 위에 제작한 소자의 경우 접촉저항은 감소하였으나 누설전류가 증가하여 전류 점멸비가 감소하였다. 그러므로, 펜타센의 두께는, 300Å∼700Å 내외, 그리고 전극은 펜타센 아래에 위치하는 것이 적합한 것으로 확인되었다.

Keywords

References

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