• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.8 no.1
• /
• pp.13-21
• /
• 1997

In this paper, the oscillator type active antenna used as an element of active phased array antenna is designed and fabricated using slot coupling. The radiating element and active circuit are fabricated on each layer respectively and coupled electromagnetically through slot on the ground plane. This structure can solve the problems such as narrow bandwidth of microstrip antenna, spurious radiation by active circuits, and spaces for integration of the feeding circuits which are caused by integrating antennas with oscillator circuits in the same layer. The active antenna in this paper, the oscillation frequency can be tuned linearly by controlling the drain bias voltage of FET. The frequency tuning range is between 12.37 GHz to 12.65 GHz when bias voltage is varied from 3V to 9V, thus frequency tuning bandwidth is 280 MHz (2.24%). The output power of antenna is uniform within 5dB over frequency tuning range. Therefore this active antenna can be used as an element of linear or planar active phased array antennas.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.4B
• /
• pp.365-371
• /
• 2002

In this paper, the fabricated power PHEMT devices for millimeter-wave that is below a gate-length of 0.2 $\mu\textrm{m}$ using electronic beam lithography technologies, and the DC and frequency characteristics and an output power characteristics were Measured at the various bias conditions. The unit process that is used in PHEMT's manufacture used that low-resistance ohmic contact, air-bridge and back-side lapping process technologies, and so on. The fabricated power PHEMT have an S521 gain of 4 dB and a maximum transconductance(gm) of 317 mS/mm, an unilateral current gain(fT) of 62 GHz, a maximum oscillation frequency(fmax) of 120 GHz at 35 GHz, and a maximum power output(Pmax) of 16 dBm, a power gain(GP) of 4 dB and a drain efficiency(DE) of 35.5 %.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.1
• /
• pp.111-116
• /
• 2006

In this paper, the image sensor using the a-Si:H TFT is proposed. The optimum amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD). TFT and photodiode both with the thin film are fabricated and form image sensor. The photodiode shows that Idark is $10^{-12}A$, Iphoto is $10^{-9}A$ and Iphoto/Idark is $10^3$, respectively. In the case of a-Si:H TFT, it indicates that Ion/Ioff is $10^6$, the drain current is a few ${\mu}A$ and Vth is $2\~4$ volts. For the analysis on the fabricated image sensor, the reverse bias of -5 voltage in ITO of photodiode and $70{\mu}sec$ pulse in the gate of TFT are applied. The image sensor with good property was conformed through the measured photo/dark current.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.5
• /
• pp.1149-1154
• /
• 2014

To observe the tunneling phenomenon of oxide semiconductor transistor, The Indium-gallum-zinc-oxide thin film transistors deposited on SiOC as a gate insulator was prepared. The interface characteristics between a dielectric and channel were changed in according to the properties of SiOC dielectric materials. The transfer characteristics of a drain-source current ($I_{DS}$) and gate-source voltage ($V_{GS}$) showed the ambipolar or unipolar features according to the Schottky or Ohmic contacts. The ambipolar transfer characteristics was obtained at a transistor with Schottky contact in a range of ${\pm}1V$ bias voltage. However, the unipolar transfer characteristics was shown in a transistor with Ohmic contact by the electron trapping conduction. Moreover, it was improved the on/off switching in a ambipolar transistor by the tunneling phenomenon.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.6
• /
• pp.1-6
• /
• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.4 s.334
• /
• pp.1-8
• /
• 2005

The increased effective impurity due to the pocket ion implantation is well blown to give rise to a reduction of the effective mobility of halo MOSFETs. However, further decrease of the effective mobility can be observed in pocket implanted MOSFETs above the mobility reduction due to the Coulomb impurity scattering and the gate bias dependency of the effective mobility can also differ from the simple model describing the mobility behavior in terms of the effective impurity. Phonon scattering and surface scattering as well as impurity Coulomb scattering are also shown to be effective in the degradation of the carrier mobility of pocket implanted MOSFETs. Using the 1-D regional approximation the effect of the distribution of the inversion charge density along the channel on the drain current is investigated. The inhomogeneous channel charge distribution due to pocket implantation is also shown to contribute to the further reduction of the effective mobility in halo MOSFETs.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.2
• /
• pp.348-354
• /
• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.61-64
• /
• 2002

We have optimally designed and implemented by a monolithic microwave integrated circuit(MMIC) the low noise amplifier(LNA) of 5.8GHz band composed of receiver front-end(RFE) in a on-board equipment system for dedicated short range communication using a depletion-mode GaAs MESFET. The LNA is provided with two active devices, matching circuits, and two drain bias circuits. Operating at a single supply of 3V and a consumption current of 18㎃, The gain at center frequency 5.8GHz is 13.4dB, Noise figure(NF) is 1.94dB, Input 3rd order intercept point(lIPS) is 3dBm, and Input return loss(5$_{11}$) and Output return loss(S$_{22}$) is -l8dB and -13.3dB, respectively. The circuit size is 1.2$\times$O.7$\textrm{mm}^2$.EX>.>.

• Journal of Advanced Navigation Technology
• /
• v.15 no.4
• /
• pp.596-601
• /
• 2011

This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2018.06a
• /
• pp.55-55
• /
• 2018

Recently, amorphous oxides such as InGaZnO (IGZO) and InZnO (IZO) as a channel layer of an oxide TFT have been attracted by advantages such as high mobility, good uniformity, and high transparency. In order to apply such an amorphous oxide TFTs to a display, the stability in various environments must be ensured. In the InGaZnO which has been studied in the past, Ga elements act as a suppressor of oxygen vacancy and result in a decreased mobility at the same time. Previous studies have been showed that the InZnO, which does not contain Ga, can achieve high mobility, but has relatively poor stability under various instability environments. In this study, the TFTs using $IZO/Al_2O_3$ double layer structure were studied. The introduction of an $Al_2O_3$ interlayer between source/drain and channel causes superior electrical characteristics and electrical stability as well as reduced contact resistance with optimally perfect ohmic contact. For the IZO and $Al_2O_3$ bilayer structures, the IZO 30nm IZO channels were prepared at $Ar:O_2=30:1$ by sputtering and the $Al_2O_3$ interlayer were depostied with various thickness by ALD at $150^{\circ}C$. The optimal sample exhibits considerably good TFT performance with $V_{th}$ of -3.3V and field effect mobility of $19.25cm^2/Vs$, and reduced $V_{th}$ shift under positive bias stress stability, compared to conventional IZO TFT. The enhanced TFT performances are closely related to the nice ohmic contact properties coming from the defect passivation of the IZO surface inducing charge traps, and we will provide the detail mechanism and model via electrical analysis and transmission line method.