• Journal of Sensor Science and Technology
• /
• v.11 no.2
• /
• pp.84-92
• /
• 2002

A $32{\times}32$ pixels foveated (linear-polar) structure retina chip with the function of local-light adaptation for edge detection has been designed and fabricated using CMOS technology. Human retina can detect a wide range of light intensity. In this study, we use the biologically-inspired visual signal processing mechanism that consists of photoreceptors, horizontal cells, and bipolar cells in order to implement the function of edge detection in the retina chip. For a local-light adaptive function, the size of receptive field is changed locally according to the input light intensity. The spatial distribution of sensing pixels in the foveated retina chip has the advantages of selective reduction of image data and good resolution in central part to carry out the elaborate image processing with still enough resolution in the outer parts. The designed chip has been fabricated using standard $0.6\;{\mu}m$ double-poly triple-metal CMOS technology and optimized using HSPICE simulator.

• Journal of Satellite, Information and Communications
• /
• v.7 no.2
• /
• pp.18-24
• /
• 2012

High current behaviors of the extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOSFET) for electrostatic discharge (ESD) protection of high voltage operating LDI (LCD Driver IC) chip are analyzed. Both the transmission line pulse (TLP) data and the thermal incorporated 2-dimensional simulation analysis demonstrate a characteristic double snapback phenomenon after triggering of biploar junction transistor (BJT) operation. Also, background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the EDNMOS devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.

• Journal of the Institute of Convergence Signal Processing
• /
• v.10 no.4
• /
• pp.289-293
• /
• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of electromagnetic engineering and science
• /
• v.8 no.3
• /
• pp.91-95
• /
• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• Journal of Astronomy and Space Sciences
• /
• v.29 no.3
• /
• pp.315-320
• /
• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• Current Optics and Photonics
• /
• v.2 no.6
• /
• pp.576-581
• /
• 2018

A new approach for identification of a microwave frequency using an integrated optical waveguide chip, combined with a phase modulator (PM) and two microring resonators (MRRs), is proposed, theoretically deduced, and verified. By wavelength tuning to set the PM under the condition of a double side band (DSB), the measurement range can be started from the dc component, and the measurement range and response slope can be adjusted by designing the radius and transmission coefficient of the MRR. Simulations reveal that the amplitude comparison function (ACF) has a monotonic relationship from dc to 32.5 GHz, with a response slope of 5.15 dB under conditions of DSB modulation, when the radius values, transmission coefficients, and the loss factors are designed respectively as $R_1=400{\mu}m$, $R_2=600{\mu}m$, $t_1=t_2=0.63$, and ${\gamma}_1={\gamma}_2=0.66$. Theoretical calculations and simulation results both indicate that this new approach has the potential to be used for measuring microwave frequencies, with the advantages of compact structure and superior reconfigurability.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.511-519
• /
• 2016

This paper proposes a CMOS 6-bit phase shifter with low RMS phase and amplitude errors for an X-band phased array antenna. The phase shifter combines a switched-path topology for coarse phase states and a switch-filter topology for fine phase states. The coarse phase shifter is composed of phase shifting elements, single-pole double-throw (SPDT), and double-pole double-throw (DPDT) switches. The fine phase shifter uses a switched LC filter. The phase coverage is $354.35^{\circ}$ with an LSB of $5.625^{\circ}$. The RMS phase error is < $6^{\circ}$ and the RMS amplitude error is < 0.45 dB at 8-12 GHz. The measured insertion loss is < 15 dB, and the return losses for input and output are > 13 dB at 8-12 GHz. The input P1dB of the phase shifter achieves > 11 dBm at 8-12 GHz. The current consumption is zero with a 1.2-V supply voltage. The chip size is $1.46{\times}0.83mm^2$, including pads.

• Journal of Satellite, Information and Communications
• /
• v.8 no.2
• /
• pp.36-43
• /
• 2013

In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.4
• /
• pp.8-13
• /
• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.103-106
• /
• 2003

An oscillatory neural network circuit has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed oscillatory neural network consists of 3 neural oscillator cells with excitatory synapses and a neural oscillator cell with inhibitory synapse. Simulations of a network of oscillators demonstrate cooperative computation. Measurements of the fabricated chip in condition of $\pm$ 2.5 V power supply is shown.