CMOS Circuit Design of a Oscillatory Neural Network

진동성 신경회로망의 CMOS 회로설계

An oscillatory neural network circuit has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed oscillatory neural network consists of 3 neural oscillator cells with excitatory synapses and a neural oscillator cell with inhibitory synapse. Simulations of a network of oscillators demonstrate cooperative computation. Measurements of the fabricated chip in condition of $\pm$ 2.5 V power supply is shown.