• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.11
• /
• pp.140-151
• /
• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.3
• /
• pp.68-76
• /
• 1985

A charge-coupled device (CCD) area image sensor has been demonstrated with an experi-mental 16$\times$16 prototype. The prototype is a vertical frame transfer charge.coupled imager using two-phase gate electrode structures. In this device, ion-implanted barriers are used for two -phase CCD, and NMOS process has been adopted. The total imaging setup consisting of optical lens, clock generators, clock drivels, staircase signal generators, and oscilloscope is easily achieved with the aid of PROM . English alphabets are displayed on the oscilloscope screen using the total imaging set-up. We measure charge transfer inefficiency and dark current for the fabricated devices.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.7 s.361
• /
• pp.16-23
• /
• 2007

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.1
• /
• pp.40-50
• /
• 2011

A two-dimensional (2D) analytical model for the potential distribution and threshold voltage of short-channel ion-implanted GaAs MESFETs operating in the sub-threshold regime has been presented. A double-integrable Gaussian-like function has been assumed as the doping distribution profile in the vertical direction of the channel. The Schottky gate has been assumed to be semi-transparent through which optical radiation is coupled into the device. The 2D potential distribution in the channel of the short-channel device has been obtained by solving the 2D Poisson's equation by using suitable boundary conditions. The effects of excess carrier generation due to the incident optical radiation in channel region have been included in the Poisson's equation to study the optical effects on the device. The potential function has been utilized to model the threshold voltage of the device under dark and illuminated conditions. The proposed model has been verified by comparing the theoretically predicted results with simulated data obtained by using the commercially available $ATLAS^{TM}$ 2D device simulator.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.161-165
• /
• 2023

This paper designed a voltage feedback driving circuit to compensate for the characteristic deviation of the Active Matrix Organic Light Emitting Diode driving Thin Film Transistor. This paper describes a stable and fast circuit by applying charge sharing and polar stabilization methods. A 12-inch Organic Light Emitting Diode with a Double Wide Ultra eXtended Graphics Array resolution creates a screen distortion problem for line parasitism, and charge sharing and polar stabilization structures were applied to solve the problem. By applying Charge Sharing, all data lines are shorted at the same time and quickly positioned as the average voltage to advance the compensated change time of the gate voltage in the next operation period. A buffer circuit and a current pass circuit were added to lower the Amplifier resistance connected to the line as a polar stabilization method. The advantage of suppressing the Ringing of the driving Thin Film Transistor can be obtained by increasing the stability. As a result, a circuit was designed to supply a stable current to the Organic Light Emitting Diode even if the characteristic deviation of the driving Thin Film Transistor occurs.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.210-215
• /
• 2017

We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

• Journal of architectural history
• /
• v.20 no.6
• /
• pp.169-184
• /
• 2011

The following research of the road network of Jeju-Eupseong during Daehan Empire period has a twofold purpose: to study some characteristics of the road network at that time; and, to restore it to the original form of that period before a newly constructed road, called Shinjakro, has been established. As an attempt to trace the old shape of Jeju-Eupseong, this study analyzed some historical factors based on the first land cadastral map which was made in 1914, including outskirts of Jeju-Eupseong; such as castle itself, castle gate, road, bridge, lots of land, etc. Then this study also tried to restore the old road network of Jeju-Eupseong, through finding the original land-lot shape in the land cadastral map. There was five Shinjakro made between 1914 and 1917. The road network before then was composed of the double east-west axes and the single north-south axis. These axes was connected to some important place of the inside of Jeju-Eupseong; such as castle gates, fountains, Gaek-sa, etc. There were many branch lines between these main axes at about 80-120m intervals. Also there was an outer road along the outer wall of castle, connected with each castle gates. Especially, the north-west axis was the baseline which divided into two large parts, a government office area and non-government area (housing and commercial street for the people). Finally, this paper examines that the road network of Jeju-Eupseong was the true result for the efficient function of the city, especially considering natural geographical conditions and environment of living of that time.

• Journal of Advanced Navigation Technology
• /
• v.20 no.5
• /
• pp.453-461
• /
• 2016

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.

• The Korean Journal of Malacology
• /
• v.28 no.3
• /
• pp.277-291
• /
• 2012

Aquaculture is challenged by a number of constraints with future efforts towards sustainable production. Global climate change has a potential damage to the sustainability by changing environmental surroundings unfavorably. The damaging parameters identified are water temperature, sea level, surface physical energy, precipitation, solar radiation, ocean acidification, and so on. Of them, temperature, mostly temperature elevation, occupies significant concern among marine ecologists and aquaculturists. Ocean acidification particularly draws shellfish aquaculturists' attention as it alters the marine chemistry, shifting the equilibrium towards more dissolved CO2 and hydrogen ions ($H^+$) and thus influencing signaling pathways on shell formation, immune system, and other biological processes. Temperature elevation by climate change is of double-sidedness: it can be an opportunistic parameter besides being a generally known damaging parameter in aquaculture. It can provide better environments for faster and longer growth for aquaculture species. It is also somehow advantageous for alleviation of aquaculture expansion pressure in a given location by opening a gate for new species and aquaculture zone expansion northward in the northern hemisphere, otherwise unavailable due to temperature limit. But in the science of climate change, the ways of influence on aquaculture are complex and ambiguous, and hence are still hard to identify and quantify. At the same time considerable parts of our knowledge on climate change effects on aquaculture are from the estimates from data of fisheries and agriculture. The consequences may be different from what they really are, particularly in the temperature region. In reality, bivalves and tunicates hung or caged in the longline system are often exposed to temperatures higher than those they encounter in nature, locally driving the farmed shellfish into an upper tolerable temperature extreme. We review recent climate change and following environment changes which can be factors or potential factors affecting shellfish aquaculture production in the temperate region.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.737-739
• /
• 2010

In this paper, the subthreshold characteristics have been alanyzed using MicroTec4.0 for double gate MOSFET(DGMOSFET). The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. The oxide thickness and channel thickness in DG MOSFET determines threshold voltage and extensively influences on Ss(Subthreshold swing). We have investigated the threshold voltage and Ss(Subthreshold swing) characteristics according to variation of channel thickness from 1nm to 3nm in this study.