A simple analytical model for deriving the threshold voltage of a SOI type symmetric DG-MOSFET

SOI형 대칭 DG MOSFET의 문턱전압 도출에 대한 간편한 해석적 모델

  • Lee, Jung-Ho (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Suh, Chung-Ha (School of Electronic & Electrical Eng., Hongik Univ.)
  • 이정호 (홍익대학교 전자전기공학부) ;
  • 서정하 (홍익대학교 전자전기공학부)
  • Published : 2007.07.25

Abstract

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

본 논문에서는 완전 공핍된 SOI형 대칭 이중게이트 MOSFET의 문턱 전압에 대한 간단한 해석적 모델을 제시하고자 실리콘 몸체 내의 전위 분포를 근사적으로 채널에 수직한 방향의 좌표에 대해 4차 다항식으로 가정하였다. 이로써 2차원 포아송 방정식을 풀어 표면 전위의 표현식을 도출하고, 이 결과로부터 드레인 전압 변화에 의한 문턱 전압의 roll-off를 비교적 정확하게 기술할 수 있는 문턱 전압의 표현식을 closed-form의 간단한 표현식으로 도출하였다. 도출된 표현식으로 모의 실험을 수행한 결과 $0.01\;[{\mu}m]$의 실리콘 채널 길이 범위까지 채널 길이에 지수적으로 감소하는 것을 보이는 비교적 정확한 결과를 얻을 수 있음을 확인하였다.

Keywords

References

  1. S. P. Sinha, A. Zaleski, D. E. Ioannou, 'Investigation of carrier generation in fully depleted enhancement and accumulation model SOI MOSFET's,' IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2413 - 2416, Dec. 1994
  2. Ni. Pei, Weiping A. V. Kammula, B. A. Minch, E. C. Kan, 'A physical compact model of DG MOSFET for mixed-signal circuit applicationspart I : model description,' IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2135 - 2143, Dec. 2004
  3. Weimin Zhang, Fossum, J. G, Mathew, L, Yang Du, 'Physical insights regarding design and performance of independent-gate FinFETs,' IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2198 - 2206, Oct. 2005 https://doi.org/10.1109/TED.2005.856184
  4. K. K. Young, 'Short-channel effect in fully depleted SOI MOSFETs,' IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399 - 402, Feb. 1989 https://doi.org/10.1109/16.19942
  5. Y. Omura, 'A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator,' IEEE Trans. Electron Devices, vol. 29, no. 11, pp. 1749–1755, Nov. 1982
  6. A. Dasgupta, S. K. Lahiri, 'A two-dimensional analytical model of threshold voltages of short-channel MOSFETs with Gaussian-doped channels,' IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 390–392, Mar. 1988
  7. Yu Tian, Ru Huang, Xing Zhang, Yangyuan Wang, 'A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET,' IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 561-568, Apr. 2005 https://doi.org/10.1109/TED.2005.844737
  8. T. J. Cunningham, R. C. Gee, E. R. Fossum, S. M. Baier, 'Deep cryogenic noise and electrical characterization of the complementary heterojunction field-effect transistor (CHFET),' IEEE Trans. Electron Device Letters, vol. 41, no. 6, pp. 888–894, Nov. 1994
  9. K. W. Terrill, C. U. Hu, P. K. Ko, 'An Analytical Model for the Channel Electric Field in MOSFET's with Graded-Drain Structures,' IEEE Trans. Electron Device Letters, vol. 5, no. 11, pp. 440–442, Nov. 1984
  10. Ge. Lixin, J. G. Fossum, 'Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs,' IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287 - 294, Feb. 2002 https://doi.org/10.1109/16.981219
  11. K. N. Ratnakumer, J. D. Meindle, 'Short-channel MOST threshold Voltage Model,' IEEE J. of Solid-state Circuits, vol. SC-17, pp. 937-947, Oct. 1982
  12. A. Ortiz-Conde, F. J. Garcia-Sanchez, S. Malobabic, 'Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETs,' IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1669 - 1672, Jul. 2005 https://doi.org/10.1109/TED.2005.850629
  13. A. Svizhenko, M. P. Anantram, T. R. Govindan, B. Biegel, 'Two-Dimensional Quantum Mechanical Modeling of Nanotransistors,' J. Appl. Phys., vol. 91, no. 4, pp. 2343 - 2354, Nov. 2002 https://doi.org/10.1063/1.1432117
  14. K. Suzuki, Y. Tosaka, T. Sugii, 'Analytical Threshold Voltage Model for Short Channel Double-Gate SO1 MOSFET's,' IEEE Trans. Electron Devices, vol. 43, no. 7, pp. 1166 - 1168, Jul. 1996 https://doi.org/10.1109/16.502429
  15. S. Satoh, H. Oka, N. Noriaki, 'Bipolar circuit simulation system using two-dimensional simulator,' Fujitsu Sci. Tech. J., vol. 24, pp. 456 -463, 1988